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128Mb: x4, x8, x16 DDR SDRAM om Features c . 4U Rate (DDR) SDRAM Double Data et MT46V32M4he8 Meg x 4 x 4 Banks - MT46V16M8 - 4 Meg x 8 x 4 Banks aS MT46V8M16 - 2 Meg x 16 x 4 Banks at .D w w Features Options Marking w
For the latest data sheet revisions, please refer to the Micron Web site: www.micron.com/sdram
* VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V * VDD = +2.6V 0.1V, VDDQ = +2.6V 0.1V (DDR 400) * Bidirectional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte) * Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle * Differential clock inputs (CK and CK#) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; centeraligned with data for WRITEs * DLL to align DQ and DQS transitions with CK * Four internal banks for concurrent operation * Data mask (DM) for masking write data (x16 has two - one per byte) * Programmable burst lengths: 2, 4, or 8 * Auto Refresh and Self Refresh Modes * Longer lead TSOP for improved reliability (OCPL) * 2.5V I/O (SSTL_2 compatible) * Concurrent auto precharge option is supported * tRAS lockout supported (tRAP = tRCD) Table 1: Configuration Addressing
Configuration Refresh Count Row Addressing Bank Addressing Column Addressing
Table 2:
Key Timing Parameters
m o .c U t4 e e h S ta a .D w w w
* Configuration 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 banks) * Plastic Package - OCPL 66-pin TSOP 66-pin TSOP (lead-free) * Timing - Cycle Time 5ns @ CL = 3 (DDR400) 6ns @ CL = 2.5 (DDR333) (TSOP only) 7.5ns @ CL = 2 (DDR266) 7.5ns @ CL = 2 (DDR266A) 7.5ns @ CL = 2.5 (DDR266B) * Self Refresh Standard Low Power Self Refresh * Temperature Rating Commercial (0C to 70C) Industrial (-40C to +85C) * Revision
32 Meg x 4 16 Meg x 8 8 Meg x 4 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 2K (A0-A9, A11) 4 Meg x 8 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 1K (A0-A9) Clock Rate CL = 2 133 MHz 133 MHz 133 MHz 100 MHz CL = 2.5 167 MHz 167 MHz 133 MHz 133 MHz CL = 3 200 MHz N/A N/A N/A Data Out Window 1.6ns 2.0ns 2.5ns 2.5ns Access Window 0.70ns 0.70ns 0.75ns 0.75ns
32M4 16M8 8M16 TG P -5B -6T -75E -75Z -75 None L None IT :D
8 Meg x 16
CL = CAS (READ) latency; minimum clock rate @ CL = 2 (-75E, -75Z), CL = 2.5 (-6, -6T, -75), and CL = 3 (-5B)
Speed Grade -5B -6T -75E/-75Z -75
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_1.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
om .c 4U et he aS at .D w w w
DQS-DQ Skew +0.40ns +0.45ns +0.50ns +0.50ns
2 Meg x 16 x 4 banks 4K 4K (A0-A11) 4 (BA0, BA1) 512 (A0-A8)
128Mb: x4, x8, x16 DDR SDRAM Marking
Figure 1: 128Mb DDR SDRAM Part Numbers
Example Part Number: MT46V8M16TG-75Z L:D
MT46V
Configuration
Package
Speed
Special Options
Temperature
REV
Configuration 32 Meg x 4 16 Meg x 8 8 Meg x 16 Package 400 mil TSOP 400 mil TSOP (lead-free) TG P IT 32M4 16M8 8M16 Operating Temp Standard Industrial Temp Special Options Standard L Low Power :D REV Revision
-5B -6 -6T -75E -75Z -75
Speed Grade tCK = 5ns, CL = 3 tCK = 6ns, CL = 2.5 tCK = 6ns, CL = 2.5 tCK = 7.5ns, CL = 2 tCK = 7.5ns, CL = 2 tCK = 7.5ns, CL = 2.5
Note:
Not all speeds and all configurations are available in all packages.
Table 3:
Marking -5B1 -6T -75E -75Z -75
Speed Grade Compatibility
PC3200 (3-3-3) Yes PC2700 (2.5-3-3) Yes Yes PC2100 (2-2-2) Yes Yes Yes PC2100 (2-3-3) Yes Yes Yes Yes PC2100 (2.5-3-3) Yes Yes Yes Yes Yes -5B -6T -75E -75Z -75 PC1600 (2-2-2) Yes Yes Yes Yes Yes -75
Notes: 1. Not available.
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_1.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM General Description
General Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2nbit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls/ pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The 128Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high, effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive option outputs are SSTL_2, Class II compatible. Notes: 1. The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. 2. Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided into two bytes, the lower byte and upper byte. For the lower byte (DQ0 through DQ7) DM refers to LDM and DQS refers to LDQS. For the upper byte (DQ8 through DQ15) DM refers to UDM and DQS refers to UDQS. 3. Complete functionality is described throughout the document and any page or diagram may have been simplified to convey a topic and may not be inclusive of all requirements. 4. Any specific requirement takes precedence over a general statement.
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_1.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Table of Contents
Table of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Functional Block Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Pin Descriptions Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Operating Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Output Drive Strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 LOAD MODE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 ACTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 BURST TERMINATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 AUTO REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 SELF REFRESH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Bank/Row Activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Power-Down (CKE Not Active) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Electrical Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Data Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16DTOC.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM List of Figures
List of Figures
Figure 1: Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: 128Mb DDR SDRAM Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 32 Meg x 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 16 Meg x 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 8 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 66-Pin TSOP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 CAS Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Extended Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Activating a Specific Row in a Specific Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK 3 . . . . . . . . . . . . . . . . . . . . . .18 READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 READ Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Consecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Random READ Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Terminating a READ Burst . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 READ to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 READ to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Consecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 WRITE to READ - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 WRITE to READ - Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 WRITE to READ - Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 WRITE to PRECHARGE - Uninterrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 WRITE to Precharge - Interrupting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 WRITE to PRECHARGE Odd Number of Data, Interrupting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Input Voltage Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 SSTL_2 Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 Derating Data Valid Window (tQH - tDQSQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64 Full Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Full Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Reduced Drive Pull-Down Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 Reduced Drive Pull-Up Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 x4, x8 Data Output Timing - tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 x16 Data Output Timing - tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 Data Output Timing - tAC and tDQSCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Initialization Flow Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 Initialize and Load Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 Auto Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 Self Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 Bank Read - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Bank Read - With Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 Bank Write - Without Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 Bank Write - With Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 Write - DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 66-Pin Plastic TSOP (400 mil) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16DLOF.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM List of Tables
List of Tables
Table 1: Table 2: Table 3: Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Table 24: Configuration Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Speed Grade Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Reserved NC Balls and Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Truth Table - Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Truth Table - DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 Truth Table - CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Truth Table - Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 Truth Table - Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75) . . . . . . . . . . . . . . .45 DC Electrical Characteristics and Operating Conditions (-5B DDR400) . . . . . . . . . . . . . . . . . . . . . . . .46 AC Input Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Clock Input Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Capacitance (x4, x8 TSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Capacitance (x16 TSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 IDD Specifications and Conditions (x4, x8; -5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 IDD Specifications and Conditions (x4, x8; -6T/-75E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 IDD Specifications and Conditions (x4, x8; -75Z/-75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52 IDD Specifications and Conditions (x16; -5B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 IDD Specifications and Conditions (x16; -6T/-75E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 IDD Specifications and Conditions (x16; -75Z/-75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 IDD Test Cycle Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 Electrical Characteristics and Recommended AC Operating Conditions (-5B) . . . . . . . . . . . . . . . . . .57 Electrical Characteristics and Recommended AC Operating Conditions (-6T/-75E). . . . . . . . . . . . .59 Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75) . . . . . . . . . . . . .60 Input Slew Rate Derating Values for Addresses and Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Input Slew Rate Derating Values for DQ, DQS, and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 Normal Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Reduced Output Drive Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16DLOT.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Functional Block Diagrams
Functional Block Diagrams
Figure 1: 32 Meg x 4
CKE CK# CK CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1
COMMAND DECODE
MODE REGISTERS
REFRESH 12 COUNTER
14 12
ROWADDRESS MUX
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK0 MEMORY ARRAY (4,096 x 1,024 x 8)
4 8 READ LATCH MUX 4 DQS GENERATOR COL0 4
CK
DATA
DLL
SENSE AMPLIFIERS 8192
DRVRS 1 DQ0 DQ3 DQS DQS 1 1 1 2 4 8 4 DATA 4 4 4 RCVRS DM 1
2 A0-A11, BA0, BA1 ADDRESS REGISTER BANK CONTROL LOGIC
I/O GATING DM MASK LOGIC
8 1 MASK WRITE FIFO & DRIVERS ck out ck in
INPUT REGISTERS
14
2
1024 (x8)
8
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH 10
11
CK COL0
1
1
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Functional Block Diagrams
Figure 2: 16 Meg x 8
CKE CK# CK CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 BANK1
COMMAND DECODE
MODE REGISTERS
REFRESH 12 COUNTER
14 12
ROWADDRESS MUX
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK0 MEMORY ARRAY (4,096 x 512 x 16)
8 16 READ LATCH MUX 8 DQS GENERATOR COL0 8
CK
DATA
DLL
SENSE AMPLIFIERS 8192
DRVRS 1 DQ0 DQ7 DQS DQS 1 1 1 2 8 16 8 DATA 8 8 8 RCVRS DM 1
2
I/O GATING DM MASK LOGIC
BANK CONTROL LOGIC
16 1 MASK WRITE FIFO & DRIVERS ck out ck in
INPUT REGISTERS
A0-A11, BA0, BA1
14
ADDRESS REGISTER
2
512 (x16)
16
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH
9
10
CK COL0
1
1
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Functional Block Diagrams
Figure 3: 8 Meg x 16
CKE CK# CK CS# WE# CAS# RAS# CONTROL LOGIC BANK3 BANK2 REFRESH COUNTER 12 BANK1
COMMAND DECODE
MODE REGISTERS
14 12
ROWADDRESS MUX
12
BANK0 ROWADDRESS LATCH & DECODER
4096
BANK0 MEMORY ARRAY (4,096 x 256 x 32)
16 32 READ LATCH MUX 16 DQS GENERATOR COL0 16
CK
DATA
DLL
SENSE AMPLIFIERS 8192
DRVRS 2 DQ0 DQ15, DQS LDQS UDQS 2 2 4 16 32 16 DATA 16 16 16 RCVRS LDM, UDM 2
2 A0-A11, BA0, BA1 ADDRESS REGISTER BANK CONTROL LOGIC
I/O GATING DM MASK LOGIC
32 2 MASK WRITE FIFO & DRIVERS ck out ck in
INPUT REGISTERS 2
14
2
256 (x32)
32
COLUMN DECODER COLUMNADDRESS COUNTER/ LATCH 8
9
CK COL0
2
1
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Pin Descriptions Tables
Pin Descriptions Tables
Table 1:
TSOP Numbers 45, 46
Pin Descriptions
Symbol CK, CK# Type Input Description Clock: CK and CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER- DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH, after which it becomes a SSTL_2 input only. Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CS# is registered HIGH. CS# provides for external bank selection on systems with multiple banks. CS# is considered part of the command code. Command Inputs: RAS#, CAS#, and WE# (along with CS#) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input-only, the DM loading is designed to match that of DQ and DQS pins. For the x16, LDM is DM for DQ0-DQ7 and UDM is DM for DQ8-DQ15. Pin 20 is a NC on x4 and x8. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command.
44
CKE
Input
24
CS#
Input
23, 22, 21 47 20 47
RAS#, CAS#, WE# DM LDM UDM
Input Input
26, 27 29, 30, 31, 32, 35, 36, 37, 38, 39, 40, 28, 41
BA0, BA1 A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11
Input Input
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
4
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128Mb: x4, x8, x16 DDR SDRAM Pin Descriptions Tables
Table 1:
TSOP Numbers 2, 4, 5, 7, 8, 10 11, 13, 54, 56, 57, 59, 60, 62, 63, 65 14, 17, 25, 42, 43, 53 2, 5, 8, 11, 56, 59, 62, 65 14, 17, 20, 25, 42, 43, 53 4, 7, 10, 13, 16, 54, 57, 60, 63 5, 11, 56, 62 14, 16, 17, 20, 25, 42, 43, 53 2, 4, 7, 8, 10, 13, 16, 54, 57, 59, 60, 63, 65 51 16 51 19, 50 3, 9, 15, 55, 61 6, 12, 52, 58, 64 1, 18, 33 34, 48, 66 49
Pin Descriptions (Continued)
Symbol DQ0-DQ2 DQ3-DQ5 DQ6-DQ8 DQ9-DQ11 DQ12-DQ14 DQ15 NC DQ0-DQ2 DQ3-DQ5 DQ6, DQ7 NC NF DQ0-DQ2 DQ3 NC NF I/O - Type I/O Description Data Input/Output: Data bus for x16
- I/O
No Connect for x16 These pins should be left unconnected. Data Input/Output: Data bus for x8
-
No Connect for x8 These pins should be left unconnected. No Function for x8 These pins should be left unconnected Data Input/Output: Data bus for x4 No Connect for x4 These pins should be left unconnected. No Function for x4 These pins should be left unconnected Data Strobe: Output with read data, input with write data. DQS is edgealigned with read data, centered in write data. It is used to capture data. For the x16, LDQS is DQS for DQ0-DQ7 and UDQS is DQS for DQ8-DQ15. Pin 16 is NU on x4 and x8. Do Not Use: Must float to minimize noise on VREF. DQ Power Supply: +2.5 0.2V (+2.6V 0.1V for DDR400). Isolated on the die for improved noise immunity. DQ Ground. Isolated on the die for improved noise immunity. Power Supply: +2.5V 0.2V (+2.6V 0.1V for DDR400). Ground. SSTL_2 reference voltage.
DQS LDQS UDQS DNU VDDQ VSSQ VDD
I/O
- Supply Supply Supply Supply Supply
VSS
VREF
Table 2:
TSOP Numbers 42,17
NOTE:
Reserved NC Balls and Pins
Symbol A12, A13 Type I Description1 Address inputs A12 and A13 for 256Mb, 512Mb and 1Gb devices. DNU for FBGA.
1. NC balls/pins not listed may also be reserved for other uses now or in the future. This table simply defines specific NC pins deemed to be of importance.
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128Mb: x4, x8, x16 DDR SDRAM Pin Assignments
Pin Assignments
Figure 4: 66-Pin TSOP (Top View)
x4 x8 x16 VDD VDD VDD NF DQ0 DQ0 VDDQ VDDQ VDDQ NF NF DQ1 DQ0 DQ1 DQ2 VSSQ VSSQ VssQ NF NF DQ3 NF DQ2 DQ4 VDDQ VDDQ VDDQ NF NF DQ5 DQ1 DQ3 DQ6 VSSQ VssQ VSSQ NF DQ7 NF NC NC NC VDDQ VDDQ VDDQ NF NF LDQS NC NC NC VDD VDD VDD DNU DNU DNU NC NC LDM WE# WE# WE# CAS# CAS# CAS# RAS# RAS# RAS# CS# CS# CS# NC NC NC BA0 BA0 BA0 BA1 BA1 BA1 A10/AP A10/AP A10/AP A0 A0 A0 A1 A1 A1 A2 A2 A2 A3 A3 A3 VDD VDD VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
x16 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS DNU VREF VSS UDM CK# CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
x8 VSS DQ7 VSSQ NF DQ6 VDDQ NF DQ5 VSSQ NF DQ4 VDDQ NF NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
x4 VSS NF VSSQ NF DQ3 VDDQ NF NF VSSQ NF DQ2 VDDQ NF NC VSSQ DQS DNU VREF VSS DM CK# CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
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128Mb: x4, x8, x16 DDR SDRAM Functional Description
Functional Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. The 128Mb DDR SDRAM is internally configured as a quadbank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls/ pins. A single read or write access for the 128Mb DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding nbit wide, one-half-clock-cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions, and device operation.
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Power must first be applied to VDD and VDDQ simultaneously, and then to VREF (and to the system VTT). VTT must be applied after VDDQ to avoid device latch-up, which may cause permanent damage to the device. VREF can be applied any time after VDDQ but is expected to be nominally coincident with VTT. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied. After CKE passes through VIH, it will transition to a SSTL_2 signal and remain as such until power is cycled. Maintaining an LVCMOS LOW level on CKE during power-up is required to ensure that the DQ and DQS outputs will be in High-Z, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a LOAD MODE REGISTER command should be issued for the extended mode register (BA1 LOW and BA0 HIGH) to enable the DLL, followed by another LOAD MODE REGISTER command to the mode register (BA0/ BA1 both LOW) to reset the DLL and to program the operating parameters. Two-hundred clock cycles are required between the DLL reset and any READ command. A PRECHARGE ALL command should then be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed (tRFC must be satisfied.) Additionally, a LOAD MODE REGISTER command for the mode register with the reset DLL bit deactivated (i.e., to program operating parameters without resetting the DLL) is required. Following these requirements, the DDR SDRAM is ready for normal operation.
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128Mb: x4, x8, x16 DDR SDRAM Functional Description Register Definition
Mode Register The mode register is used to define the specific mode of operation of the DDR SDRAM. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in Figure 5 on page 9. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 specify the operating mode. Burst Length Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable, as shown in Figure 5. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1-Ai when BL = 2, by A2-Ai when BL = 4, and by A3-Ai when BL = 8 (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts. Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 3, Burst Definition, on page 10.
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128Mb: x4, x8, x16 DDR SDRAM Functional Description
Figure 5: Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 0* 0* Operating Mode * M13 and M12 (BA1 and BA0) must be "0, 0" to select the base mode register (vs. the extended mode register).
7
6543210 CAS Latency BT Burst Length
Mode Register (Mx)
M2 M1 M0 Burst Length 0 0 0 0 1 1 1 1 M3 0 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved Burst Type Sequential Interleaved DDR400 CAS Latency Reserved Reserved 2 3 Reserved Reserved 2.5 Reserved
M6 M5 M4 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved 2 Reserved Reserved Reserved 2.5 Reserved M6-M0 Valid Valid -
M11 M10 M9 M8 M7 0 0 0 0 0 0 0 1 0 0 -
Operating Mode Normal Operation Normal Operation/Reset DLL All other states reserved
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128Mb: x4, x8, x16 DDR SDRAM Functional Description
Table 3: Burst Definition
Order of Accesses within a Burst Burst Length 2 Starting Column Address A0 0 1 A0 0 1 0 1 A0 0 1 0 1 0 1 0 1 Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
4
8
A2 0 0 0 0 1 1 1 1
A1 0 0 1 1 A1 0 0 1 1 0 0 1 1
Notes: 1. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 2. For BL = 2, A1-Ai select the two data-element block; A0 selects the first access within the block. 3. For BL = 4, A2-Ai select the four data-element block; A0-A1 select the first access within the block. 4. For BL = 8, A3-Ai select the eight data-element block; A0-A2 select the first access within the block.
Read Latency The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2, 2.5, or 3 (DDR400 only) clocks, as shown in Figure 6. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. Table 4, CAS Latency (CL), on page 11 indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used, as unknown operation or incompatibility with future versions may result.
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128Mb: x4, x8, x16 DDR SDRAM Functional Description
Figure 6: CAS Latency
T0 CK# CK COMMAND
READ NOP NOP NOP
T1
T2
T2n
T3
T3n
CL = 2
DQS DQ T0 T1 T2 T2n T3 T3n
CK# CK COMMAND
READ
NOP
NOP
NOP
CL = 2.5
DQS DQ T0 CK# CK COMMAND
READ NOP NOP NOP
T1
T2
T3
T3n
CL = 3
DQS DQ
BL = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA DON'T CARE
Table 4:
CAS Latency (CL)
Allowable Operating Clock Frequency (MHz) Speed -5B -6T -75E -75Z -75 CL = 2 75 f 133 75 f 133 75 f 133 75 f 133 75 f 100 CL = 2.5 75 f 167 75 f 167 75 f 133 75 f 133 75 f 133 CL = 3 133 f 200 - - - -
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128Mb: x4, x8, x16 DDR SDRAM Functional Description
Operating Mode The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7-A11 each set to zero, and bits A0-A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9-A11 each set to zero, bit A8 set to one, and bits A0-A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and reserved states should not be used, as unknown operation or incompatibility with future versions may result.
Extended Mode Register
The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable, and output drive strength. These functions are controlled via the bits shown in Figure 7. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Output Drive Strength The normal drive strength for all outputs are specified to be SSTL2, Class II. The x16 supports a programmable option for reduced drive. This option is intended for the support of the lighter load and/or point-to-point environments. The selection of the reduced drive strength will alter the DQ pins and DQS pins from SSTL2, Class II drive strength to a reduced drive strength, which is approximately 54 percent of the SSTL2, Class II drive strength. DLL Enable/Disable When the part is running without the DLL enabled, device functionality may be altered. The DLL must be enabled for normal operation. DLL enable is required during powerup initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, 200 clock cycles must occur before a READ command can be issued.
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128Mb: x4, x8, x16 DDR SDRAM Functional Description
Figure 7: Extended Mode Register Definition
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Address Bus
13 12 11 10 9 8 7 6 5 Operating Mode 01 11
4
3
2
1
0
DS DLL
Extended Mode Register (Ex)
E0 0 1 E12 0 1 E11 E10 E9 E8 E7 E6 E5 E4 E3 E23 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - E1, E0 Valid -
DLL Enable Disable Drive Strength Normal Reduced
Operating Mode Reserved Reserved
Notes: 1. E13 and E12 (BA1 and BA0) must be "0, 1" to select the extended mode register vs. the base mode register. 2. The reduced drive strength option is not supported on the x4 and x8 versions, and is only available on the x16 version. 3. The QFC# option is not supported.
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128Mb: x4, x8, x16 DDR SDRAM Commands
Commands
Table 5 and Table 6 provide a quick reference of available commands. This is followed by a verbal description of each command. Two additional Truth Tables--Table 8 on page 41, and Table 9 on page 43--appear following "Operations" on page 17, and provide current state/next state information. Table 5: Truth Table - Commands
Notes 1 and 10 apply to all commands Name (Function) DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER CS# H L L L L L L L L RAS# X H L H H H L L L CAS# X H H L L H H L L WE# X H H H L L L H L ADDR X X Bank/Row Bank/Col Bank/Col X Code X Op-Code Notes 9 9 3 4 4 8 5 6, 7 2
Notes: 1. CKE is HIGH for all commands shown except SELF REFRESH. 2. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0-A11 provide the op-code to be written to the selected mode register. 3. BA0-BA1 provide bank address and A0-A11 provide row address. 4. BA0-BA1 provide bank address; A0-Ai provide column address, (where i = 8 for x16, i = 9 for x8, and i = 9,11 for x4) A10 HIGH enables the auto precharge feature (non persistent), and A10 LOW disables the auto precharge feature. 5. A10 LOW: BA0-BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0-BA1 are "Don't Care." 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; for within the self refresh mode all inputs and I/Os are "Don't Care" except for CKE. 8. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read bursts with auto precharge enabled and for WRITE bursts. 9. DESELECT and NOP are functionally interchangeable. 10. All states and sequences not shown are illegal or reserved.
Table 6:
Truth Table - DM Operation
Note 1 applies to all commands Name (Function) Write Enable Write Inhibit DM L H DQ Valid X
Notes: 1. Used to mask write data; provided coincident with the corresponding data.
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128Mb: x4, x8, x16 DDR SDRAM Commands DESELECT
The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR SDRAM. The DDR SDRAM is effectively deselected. Operations already in progress are not affected.
NO OPERATION (NOP)
The NO OPERATION (NOP) command is used to instruct the selected DDR SDRAM to perform a NOP (CS# is LOW with RAS#, CAS#, and WE# are HIGH). This prevents unwanted commands from being registered during idle or wait states. Operations already in progress are not affected.
LOAD MODE REGISTER
The mode registers are loaded via inputs A0-A11. See mode register descriptions in the Register Definition section. The LOAD MODE REGISTER command can only be issued when all banks are idle, and a subsequent executable command cannot be issued until t MRD is met.
ACTIVE
The ACTIVE command is used to open (or activate) a row in a particular bank for a subsequent access. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-A11 selects the row. This row remains active (or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command must be issued before opening a different row in the same bank.
READ
The READ command is used to initiate a burst read access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai (where i = 8 for x16, 9 for x8, or 9, 11 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the READ burst; if auto precharge is not selected, the row will remain open for subsequent accesses.
WRITE
The WRITE command is used to initiate a burst write access to an active row. The value on the BA0, BA1 inputs selects the bank, and the address provided on inputs A0-Ai (where i = 8 for x16, 9 for x8, or 9, 11 for x4) selects the starting column location. The value on input A10 determines whether or not auto precharge is used. If auto precharge is selected, the row being accessed will be precharged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If a given DM signal is registered LOW, the corresponding data will be written to memory; if the DM signal is registered HIGH, the corresponding data inputs will be ignored, and a WRITE will not be executed to that byte/ column location.
PRECHARGE
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks. The bank (s) will be available for a subsequent row access a specified time (tRP) after the precharge command is issued. Except in the case of concurrent auto precharge, where a READ or WRITE command to a different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any other timing parameters. Input A10 determines whether one or all banks are to be
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128Mb: x4, x8, x16 DDR SDRAM Commands
precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. Otherwise BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. A PRECHARGE command will be treated as a NOP if there is no open row in that bank (idle state), or if the previously open row is already in the process of precharging.
Auto Precharge
Auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. This is accomplished by using A10 to enable auto precharge in conjunction with a specific READ or WRITE command. A precharge of the bank/row that is addressed with the READ or WRITE command is automatically performed upon completion of the READ or WRITE burst. Auto precharge is nonpersistent in that it is either enabled or disabled for each individual READ or WRITE command. This device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. Auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This "earliest valid stage" is determined as if an explicit PRECHARGE command was issued at the earliest possible time, without violating tRAS (MIN), as described for each burst type in"Operations" on page 17. The user must not issue another command to the same bank until the precharge time (tRP) is completed.
BURST TERMINATE
The BURST TERMINATE command is used to truncate read bursts (with auto precharge disabled). The most recently registered READ command prior to the BURST TERMINATE command will be truncated, as shown in "Operations" on page 17. The open page which the READ burst was terminated from remains open.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the DDR SDRAM and is analogous to CAS#-BEFORE-RAS# (CBR) refresh in FPM/EDO DRAMs. This command is nonpersistent, so it must be issued each time a REFRESH is required. All banks must be idle before an AUTO REFRESH command is issued. The addressing is generated by the internal refresh controller. This makes the address bits a "Don't Care" during an AUTO REFRESH command. The 128Mb DDR SDRAM requires AUTO REFRESH cycles at an average interval of 15.625s (maximum). To allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM, meaning that the maximum absolute interval between any AUTO REFRESH command and the next AUTO REFRESH command is 9 x 15.625s (140.6s). Note the JEDEC specifications only allows 8 x 15.625s, thus the Micron specification exceeds the JEDEC requirement by one clock. This maximum absolute interval is to allow future support for DLL updates internal to the DDR SDRAM to be restricted to AUTO REFRESH cycles, without allowing excessive drift in tAC between updates. Although not a JEDEC requirement, to provide for future functionality features, CKE must be active (HIGH) during the AUTO REFRESH period. The AUTO REFRESH period begins when the AUTO REFRESH command is registered and ends tRFC later.
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128Mb: x4, x8, x16 DDR SDRAM Operations SELF REFRESH
The SELF REFRESH command can be used to retain data in the DDR SDRAM, even if the rest of the system is powered down. When in the self refresh mode, the DDR SDRAM retains data without external clocking. The SELF REFRESH command is initiated like an AUTO REFRESH command except CKE is disabled (LOW). The DLL is automatically disabled upon entering SELF REFRESH and is automatically enabled upon exiting SELF REFRESH (200 clock cycles must then occur before a READ command can be issued). Input signals except CKE are "Don't Care" during SELF REFRESH. VREF voltage is also required for full duration of the SELF REFRESH cycle. The procedure for exiting SELF REFRESH requires a sequence of commands. First, CK and CK# must be stable prior to CKE going back HIGH. Once CKE is HIGH, the DDR SDRAM must have NOP commands issued for tXSNR because time is required for the completion of any internal refresh in progress. A simple algorithm for meeting both REFRESH and DLL requirements is to apply NOPs for tXSNR time, then a DLL RESET and NOPs for 200 additional clock cycles before applying any other command.
Operations
Bank/Row Activation
Before any READ or WRITE commands can be issued to a bank within the DDR SDRAM, a row in that bank must be "opened." This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated, as shown in Figure 8. After a row is opened with an ACTIVE command, a READ or WRITE command may be issued to that row, subject to the tRCD specification. tRCD (MIN) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the ACTIVE command on which a READ or WRITE command can be entered. For example, a tRCD specification of 20ns with a 133 MHz clock (7.5ns period) results in 2.7 clocks rounded to 3. This is reflected in Figure 9, which covers any case where 2 < tRCD (MIN)/tCK 3. (Figure 9 also shows the same case for tRCD; the same procedure is used to convert other specification limits from time units to clock cycles). A subsequent ACTIVE command to a different row in the same bank can only be issued after the previous active row has been "closed" (precharged). The minimum time interval between successive ACTIVE commands to the same bank is defined by tRC. A subsequent ACTIVE command to another bank can be issued while the first bank is being accessed, which results in a reduction of total row-access overhead. The minimum time interval between successive ACTIVE commands to different banks is defined by tRRD.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 8: Activating a Specific Row in a Specific Bank
CK# CK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A11
RA
BA0, BA1
BA
RA = Row Address BA = Bank Address
Figure 9:
Example: Meeting tRCD (tRRD) MIN When 2 < tRCD (tRRD) MIN/tCK 3
T0 T1 T2 T3 T4 T5 T6 T7
CK# CK COMMAND
ACT NOP NOP ACT NOP NOP RD/WR NOP
A0-A11
Row
Row
Col
BA0, BA1
Bank x
Bank y
Bank y
tRRD
tRCD
DON'T CARE
READs
READ bursts are initiated with a READ command, as shown in Figure 10 on page 20. The starting column and bank addresses are provided with the READ command and auto precharge is either enabled or disabled for that burst access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst. Note: For the READ commands used in the following illustrations, auto precharge is disabled. During READ bursts, the valid data-out element from the starting column address will be available following the CAS latency after the READ command. Each subsequent dataout element will be valid nominally at the next positive or negative clock edge (i.e., at the
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128Mb: x4, x8, x16 DDR SDRAM Operations
next crossing of CK and CK#). Figure 11 on page 21 shows general timing for each possible CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial LOW state on DQS is known as the read preamble; the LOW state coincident with the last data-out element is known as the read postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs will go High-Z. A detailed explanation of tDQSQ (valid data-out skew), tQH (data-out window hold), the valid data window are depicted in Figure 38 on page 70 and Figure 39 on page 71. A detailed explanation of tDQSCK (DQS transition skew to CK) and tAC (data-out transition skew to CK) is depicted in Figure 40 on page 72. Data from any READ burst may be concatenated with or truncated with data from a subsequent READ command. In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new READ command should be issued x cycles after the first READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 12 on page 22. A READ command can be initiated on any clock cycle following a previous READ command. Nonconsecutive read data is shown for illustration in Figure 13 on page 23. Full-speed random read accesses within a page (or pages) can be performed as shown in Figure 14 on page 24. Data from any READ burst may be truncated with a BURST TERMINATE command, as shown in Figure 15 on page 25. The BURST TERMINATE latency is equal to the read (CAS) latency, i.e., the BURST TERMINATE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Data from any READ burst must be completed or truncated before a subsequent WRITE command can be issued. If truncation is necessary, the BURST TERMINATE command must be used, as shown in Figure 16 on page 26. The tDQSS (NOM) case is shown; the t DQSS (MAX) case has a longer bus idle time. (tDQSS [MIN] and tDQSS [MAX] are defined in the section on WRITEs.) A READ burst may be followed by, or truncated with, a PRECHARGE command to the same bank provided that auto precharge was not activated. The PRECHARGE command should be issued x cycles after the READ command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). This is shown in Figure 17 on page 27. Following the PRECHARGE command, a subsequent command to the same bank cannot be issued until both tRAS and tRP has been met. Note that part of the row precharge time is hidden during the access of the last data elements.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 10: READ Command
CK# CK CKE CS# HIGH
RAS# CAS#
WE# x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 x8: A11 x16: A9, A11
EN AP CA
A10
DIS AP
BA0,1
BA
CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge DON'T CARE
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 11: READ Burst
T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n NOP NOP NOP NOP NOP
T1
T2
T2n
T3
T3n
T4
T5
CL = 2 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n NOP NOP NOP NOP NOP DO n
T1
T2
T2n
T3
T3n
T4
T5
CL = 2.5 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n NOP NOP NOP NOP NOP DO n
T1
T2
T3
T3n
T4
T4n
T5
CL = 3 DQS DQ
DO n
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4.
DO n = data-out from column n. BL = 4. Three subsequent elements of data-out appear in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 12: Consecutive READ Bursts
T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP READ Bank, Col b NOP NOP NOP
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CL = 2 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP READ Bank, Col b NOP NOP NOP DO n DO b
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CL = 2.5 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP READ Bank, Col b NOP NOP NOP DO n DO b
T1
T2
T3
T3n
T4
T4n
T5
T5n
CL = 3 DQS DQ
DO n DO b
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4.
DO n (or b) = data-out from column n (or column b). BL = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). Three subsequent elements of data-out appear in the programmed order following DO n. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. 5. Shown with nominal tAC, tDQSCK, and tDQSQ. 6. Example applies only when READ commands are issued to same device.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 13: Nonconsecutive READ Bursts
T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP
T1
T2
T2n
T3
T3n
T4
T5
T5n
T6
CL = 2 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP DO n DO b
T1
T2
T2n
T3
T3n
T4
T5
T5n
T6
CL = 2.5 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n NOP NOP READ Bank, Col b NOP NOP NOP DO n DO b
T1
T2
T3
T3n
T4
T4n
T5
T6
CL = 3 DQS DQ
DO n DO b
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4.
DO n (or b) = data-out from column n (or column b). BL = 4 or 8 (if 4, the bursts are concatenated; if 8, the second burst interrupts the first). Three subsequent elements of data-out appear in the programmed order following DO n. Three (or seven) subsequent elements of data-out appear in the programmed order following DO b. 5. Shown with nominal tAC, tDQSCK, and tDQSQ.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 14: Random READ Accesses
T0 CK# CK COMMAND ADDRESS
READ Bank, Col n READ Bank, Col x READ Bank, Col b READ Bank, Col g NOP NOP
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CL = 2 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n READ Bank, Col x READ Bank, Col b READ Bank, Col g NOP NOP DO n DO n' DO x DO x' DO b DO b' DO g
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
CL = 2.5 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank, Col n READ Bank, Col x READ Bank, Col b READ Bank, Col g NOP NOP DO n DO n' DO x DO x' DO b DO b'
T1
T2
T3
T3n
T4
T4n
T5
T5n
CL = 3 DQS DQ
DO n DO n' DO x DO x' DO b DO b'
DON'T CARE
TRANSITIONING DATA
Notes: 1. DO n (or x or b or g) = data-out from column n (or column x or column b or column g). 2. BL = 2, 4, or 8 (if 4 or 8, the following burst interrupts the previous). 3. An n' or x' or b' or g' indicates the next data-out following DO n or DO x or DO b or DO g, respectively. 4. READs are to an active row in any bank. 5. Shown with nominal tAC, tDQSCK, and tDQSQ.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 15: Terminating a READ Burst
T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n BST5 NOP NOP NOP NOP
T1
T2
T2n
T3
T4
T5
CL = 2 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n BST5 NOP NOP NOP NOP DO n
T1
T2
T2n
T3
T4
T5
CL = 2.5 DQS DQ T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n BST5 NOP NOP NOP NOP DO n
T1
T2
T3
T3n
T4
T5
CL = 3 DQS DQ
DO n
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4. 5.
DO n = data-out from column n. BL = 4 or 8. Subsequent element of data-out appears in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. BST = BURST TERMINATE command, page remains open.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 16: READ to WRITE
T0 CK# CK COMMAND ADDRESS
READ Bank, Col n BST7 NOP WRITE Bank, Col b NOP NOP
T1
T2
T2n
T3
T4
T4n
T5
T5n
CL = 2 DQS DQ DM T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n BST7 NOP DO n
tDQSS (NOM)
DI b
T1
T2
T2n
T3
T3n
T4
T5
T5n
NOP
WRITE Bank, Col b
NOP
CL = 2.5 DQS DQ DM T0 CK# CK COMMAND ADDRESS
READ Bank a, Col n BST7 NOP NOP WRITE Bank, Col b DO n
tDQSS (NOM)
DI b
T1
T2
T3
T3n
T4
T5
T5n
NOP
CL = 3 DQS DQ DM DON'T CARE
DO n
tDQSS (NOM)
DI b
TRANSITIONING DATA
Notes: 1. DO n = data-out from column n. 2. DI b = data-in from column b. 3. BL = 4 in the cases shown (applies for bursts of 8 as well; if BL = 2, the BST command shown can be NOP). 4. One subsequent element of data-out appears in the programmed order following DO n. 5. Data-in elements are applied following DI b in the programmed order. 6. Shown with nominal tAC, tDQSCK, and tDQSQ. 7. BST = BURST TERMINATE command, page remains open.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 17: READ to PRECHARGE
T0 CK# CK COMMAND6 ADDRESS
READ Bank a, Col n NOP PRE Bank a, (a or all) NOP NOP ACT7 Bank a, Row
T1
T2
T2n
T3
T3n
T4
T5
CL = 2 DQS DQ T0 CK# CK COMMAND6 ADDRESS
READ Bank a, Col n NOP PRE Bank a, (a or all) NOP DO n
tRP
T1
T2
T2n
T3
T3n
T4
T5
NOP
ACT7 Bank a, Row
CL = 2.5 DQS DQ T0 CK# CK COMMAND6 ADDRESS
READ Bank a, Col n NOP PRE Bank a, (a or all) NOP DO n
tRP
T1
T2
T3
T3n
T4
T4n
T5
NOP
ACT7 Bank a, Row
CL = 3 DQS DQ
tRP
DO n
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4. 5.
DO n = data-out from column n. BL = 4, or an interrupted burst of 8. Three subsequent elements of data-out appear in the programmed order following DO n. Shown with nominal tAC, tDQSCK, and tDQSQ. READ to PRECHARGE equals two clocks, which allows two data pairs of data-out; it is also assumed that tRAS (MIN) is met. 6. A READ command with AUTO-PRECHARGE enabled, provided tRAS (MIN) is met, would cause a precharge to be performed at x number of clock cycles after the READ command, where x = BL / 2. 7. An active command to the same bank is only allowed if tRC (MIN) has been satisfied. 8. PRE = PRECHARGE command; ACT = ACTIVE command.
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128Mb: x4, x8, x16 DDR SDRAM Operations WRITEs
WRITE bursts are initiated with a WRITE command, as shown in Figure 18. The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access. If auto precharge is enabled, the row being accessed is precharged at the completion of the burst and after the tWR time. Note: For the WRITE commands used in the following illustrations, auto precharge is disabled. During WRITE bursts, the first valid data-in element will be registered on the first rising edge of DQS following the WRITE command, and subsequent data elements will be registered on successive edges of DQS. The LOW state on DQS between the WRITE command and the first rising edge is known as the write preamble; the LOW state on DQS following the last data-in element is known as the write postamble. The time between the WRITE command and the first corresponding rising edge of DQS (tDQSS) is specified with a relatively wide range (from 75 percent to 125 percent of one clock cycle and 72 percent to 128 percent of one clock cycle for DDR400). All of the
WRITE diagrams show the nominal case, and where the two extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX]) might not be intuitive, they have also been included. Figure 19 on page 30 shows the nominal case and the extremes of tDQSS for a burst of 4. Upon completion of a burst, assuming no other commands have been initiated, the DQ will remain High-Z and any additional input data will be ignored.
Data for any WRITE burst may be concatenated with or truncated with a subsequent WRITE command. In either case, a continuous flow of input data can be maintained. The new WRITE command can be issued on any positive edge of clock following the previous WRITE command. The first data element from the new burst is applied after either the last element of a completed burst or the last desired data element of a longer burst which is being truncated. The new WRITE command should be issued x cycles after the first WRITE command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). Figure 20 on page 31 shows concatenated bursts of 4. An example of nonconsecutive WRITEs is shown in Figure 21 on page 31. Full-speed random write accesses within a page or pages can be performed, as shown in Figure 22 on page 32.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 18: WRITE Command
CK# CK CKE CS# RAS# CAS# HIGH
WE# x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 x8: A11 x16: A9, A11
EN AP
CA
A10
DIS AP
BA0,1
BA
DON'T CARE
CA = Column Address BA = Bank Address EN AP = Enable Auto Precharge DIS AP = Disable Auto Precharge
Data for any WRITE burst may be followed by a subsequent READ command. To follow a WRITE without truncating the WRITE burst, tWTR should be met, as shown in Figure 23 on page 33. Data for any WRITE burst may be truncated by a subsequent READ command, as shown in Figure 24 on page 34. Note that only the data-in pairs that are registered prior to the tWTR period are written to the internal array, and any subsequent data-in should be masked with DM, as shown in Figure 25 on page 35. Data for any WRITE burst may be followed by a subsequent PRECHARGE command. To follow a WRITE without truncating the WRITE burst, tWR should be met, as shown in Figure 26 on page 36. Data for any WRITE burst may be truncated by a subsequent PRECHARGE command, as shown in Figure 27 on page 37 and Figure 28 on page 38. Note that only the data-in pairs that are registered prior to the tWR period are written to the internal array, and any subsequent data-in should be masked with DM as shown in Figures 27 and 28. After the PRECHARGE command, a subsequent command to the same bank cannot be issued until tRP is met.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 19: WRITE Burst
T0 CK# CK COMMAND ADDRESS
tDQSS (NOM) WRITE Bank a, Col b NOP NOP NOP
T1
T2
T2n
T3
DQS DQ DM
tDQSS (MIN)
tDQSS
DI b
DQS DQ DM
tDQSS (MAX)
tDQSS
DI b
DQS DQ DM
tDQSS
DI b
DON'T CARE
TRANSITIONING DATA
Notes: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. A10 is LOW with the WRITE command (auto precharge is disabled).
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 20: Consecutive WRITE to WRITE
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T3n T4 T4n T5
WRITE
NOP
WRITE
NOP
NOP
NOP
ADDRESS
tDQSS (NOM)
Bank, Col b tDQSS
Bank, Col n
DQS
DI b DI n
DQ DM
DON'T CARE
TRANSITIONING DATA
Notes: 1. DI b, etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. Three subsequent elements of data-in are applied in the programmed order following DI n. 4. An uninterrupted burst of 4 is shown. 5. Each WRITE command may be to any bank.
Figure 21:
Nonconsecutive WRITE to WRITE
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T4 T4n T5 T5n
WRITE
NOP
NOP
WRITE
NOP
NOP
ADDRESS
tDQSS (NOM)
Bank, Col b tDQSS
Bank, Col n
DQS
DI b DI n
DQ DM
DON'T CARE
TRANSITIONING DATA
Notes: 1. DI b, etc. = data-in for column b, etc. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. Three subsequent elements of data-in are applied in the programmed order following DI n. 4. An uninterrupted burst of 4 is shown.
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128Mb: x4, x8, x16 DDR SDRAM Operations
5. Each WRITE command may be to any bank.
Figure 22:
Random WRITE Cycles
T0 CK# CK COMMAND T1 T1n T2 T2n T3 T3n T4 T4n T5 T5n
WRITE
WRITE
WRITE
WRITE
WRITE
NOP
ADDRESS
Bank, Col b
Bank, Col x
Bank, Col n
Bank, Col a
Bank, Col g
tDQSS (NOM)
DQS
DI b DI b' DI x DI x' DI n DI n' DI a DI a' DI g DI g'
DQ DM
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4.
DI b, etc. = data-in for column b, etc. b', etc. = the next data-in following DI b, etc., according to the programmed burst order. Programmed burst length = 2, 4, or 8 in cases shown. Each WRITE command may be to any bank.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 23: WRITE to READ - Uninterrupting
T0 CK# CK COMMAND
WRITE NOP NOP NOP tWTR READ NOP NOP
T1
T1n
T2
T2n
T3
T4
T5
T6
T6n
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
DQS DQ DM
tDQSS (MIN) tDQSS DI b DO n
CL = 2
DQS DQ DM
tDQSS (MAX) tDQSS DI b DO n
CL = 2
DQS DQ DM
DI b DO n
DON'T CARE
TRANSITIONING DATA
Notes: 1. DI b = data-in for column b, DO n = data-out for column n. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. tWTR is referenced from the first positive CK edge after the last data-in pair. 5. The READ and WRITE commands are to same device. However, the READ and WRITE commands may be to different devices, in which case tWTR is not required and the READ command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled).
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 24: WRITE to READ - Interrupting
T0 CK# CK COMMAND
WRITE NOP NOP tWTR READ NOP NOP NOP
T1
T1n
T2
T2n
T3
T3n
T4
T5
T5n
T6
T6n
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
DQS DQ DM
tDQSS (MIN) tDQSS DI b DO n
CL = 2
DQS DQ DM
tDQSS (MAX) tDQSS DI b DO n
CL = 2
DQS DQ DM
DI b DO n
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4. 5. 6. 7.
DI b = data-in for column b, DO n = data-out for column n. An interrupted burst of 4 is shown; two data elements are written. One subsequent element of data-in is applied in the programmed order following DI b. t WTR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T2 and T2n (nominal case) to register DM. If the burst of 8 was used, DM and DQS would be required at T3 and T3n because the READ command would not mask these two data elements.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 25: WRITE to READ - Odd Number of Data, Interrupting
T0 CK# CK COMMAND
WRITE NOP NOP tWTR READ NOP NOP NOP
T1
T1n
T2
T2n
T3
T3n
T4
T5
T5n
T6
T6n
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
Bank a, Col n
CL = 2
DQS DQ DM
tDQSS (MIN) tDQSS DI b DO n
CL = 2
DQS DQ DM
tDQSS (MAX) tDQSS DI b DO n
CL = 2
DQS DQ DM
DI b DO n
DON'T CARE
TRANSITIONING DATA
Notes: 1. DI b = data-in for column b, DO n = data-out for column n. 2. An interrupted burst of 4 is shown; one data element is written. 3. tWTR is referenced from the first positive CK edge after the last desired data-in pair (not the last two data elements). 4. A10 is LOW with the WRITE command (auto precharge is disabled). 5. DQS is required at T1n, T2, and T2n (nominal case) to register DM. 6. If the burst of 8 was used, DM and DQS would be required at T3 - T3n because the READ command would not mask these data elements.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 26: WRITE to PRECHARGE - Uninterrupting
T0 CK# CK COMMAND
WRITE NOP NOP NOP tWR NOP PRE7 tRP Bank, (a or all) NOP
T1
T1n
T2
T2n
T3
T4
T5
T6
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
DQS DQ DM
tDQSS (MIN) tDQSS DI b
DQS DQ DM
tDQSS (MAX) tDQSS DI b
DQS DQ DM
DI b
DON'T CARE
TRANSITIONING DATA
Notes: 1. DI b = data-in for column b. 2. Three subsequent elements of data-in are applied in the programmed order following DI b. 3. An uninterrupted burst of 4 is shown. 4. tWR is referenced from the first positive CK edge after the last data-in pair. 5. The PRECHARGE and WRITE commands are to the same device. However, the PRECHARGE and WRITE commands may be to different devices, in which case tWR is not required and the PRECHARGE command could be applied earlier. 6. A10 is LOW with the WRITE command (auto precharge is disabled). 7. PRE = PRECHARGE command.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 27: WRITE to Precharge - Interrupting
T0 CK# CK COMMAND
WRITE NOP NOP tWR NOP PRE8 NOP tRP Bank, (a or all) NOP
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
DQS DQ DM
tDQSS (MIN) tDQSS DI b
DQS DQ DM
tDQSS (MAX) tDQSS DI b
DQS DQ DM
DI b
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4. 5. 6. 7. 8.
DI b = data-in for column b. Subsequent element of data-in is applied in the programmed order following DI b. An interrupted burst of 8 is shown; two data elements are written. tWR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T4 and T4n (nominal case) to register DM. If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n. PRE = PRECHARGE command.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Figure 28: WRITE to PRECHARGE Odd Number of Data, Interrupting
T0 CK# CK COMMAND
WRITE NOP NOP tWR NOP PRE7 NOP tRP Bank, (a or all) NOP
T1
T1n
T2
T2n
T3
T3n
T4
T4n
T5
T6
ADDRESS
tDQSS (NOM)
Bank a, Col b tDQSS
DQS DQ DM
tDQSS (MIN) tDQSS DI b
DQS DQ DM
tDQSS (MAX) tDQSS DI b
DQS DQ DM
DI b
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4. 5. 6. 7.
DI b = data-in for column b. An interrupted burst of 8 is shown; one data element is written. tWR is referenced from the first positive CK edge after the last data-in pair. A10 is LOW with the WRITE command (auto precharge is disabled). DQS is required at T4 and T4n (nominal case) to register DM. If the burst of 4 was used, DQS and DM would not be required at T3, T3n, T4 and T4n. PRE = PRECHARGE command.
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128Mb: x4, x8, x16 DDR SDRAM Operations PRECHARGE
The PRECHARGE command as shown in Figure 29, is used to deactivate the open row in a particular bank or the open row in all banks. The bank (s) will be available for a subsequent row access some specified time (tRP) after the PRECHARGE command is issued. Input A10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs BA0, BA1 select the bank. When all banks are to be precharged, inputs BA0, BA1 are treated as "Don't Care." Once a bank has been precharged, it is in the idle state and must be activated prior to any READ or WRITE commands being issued to that bank. Figure 29: PRECHARGE Command
CK# CK CKE CS# HIGH
RAS#
CAS#
WE#
A0-A9, A11
ALL BANKS
A10
ONE BANK
BA0,1
BA
BA = Bank Address (if A10 is LOW; otherwise "Don't Care") DON'T CARE
Power-Down (CKE Not Active)
Unlike SDR SDRAMs, DDR SDRAMs require CKE to be active at all times an access is in progress, from the issuing of a READ or WRITE command until completion of the access. Thus a clock suspend is not supported. For READs, an access completion is defined when the read postamble is satisfied; for WRITEs, an access completion is defined when the write recovery time (tWR) is satisfied. Power-down, as shown in Figure 30 on page 40, is entered when CKE is registered LOW and all Table 7 (page 40)criteria are met. If power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. Entering powerdown deactivates the input and output buffers, excluding CK, CK#, and CKE. For maximum power savings, the DLL is frozen during precharge power-down mode. Exiting
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128Mb: x4, x8, x16 DDR SDRAM Operations
power-down requires the device to be at the same voltage and frequency as when it entered power-down. However, power-down duration is limited by the refresh requirements of the device (tREFC). While in power-down, CKE LOW and a stable clock signal must be maintained at the inputs of the DDR SDRAM, while all other input signals are "Don't Care." The powerdown state is synchronously exited when CKE is registered HIGH (in conjunction with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later. Figure 30: Power-Down
T0 CK# CK
tIS
T1
T2 ( (
Ta0
Ta1
Ta2
)) (( ))
tIS
CKE
(( ))
COMMAND
VALID
NOP
(( )) (( ))
NOP
VALID
VALID
No READ/WRITE access in progress
Enter power-down mode
Exit power-down mode DON'T CARE
Table 7:
CKEn-1 L L H
Truth Table - CKE
Notes: 1-6 CKEn L H L Current State Power-Down Self Refresh Power-Down Self Refresh All Banks Idle Bank (s) Active All Banks Idle Commandn X X DESELECT or NOP DESELECT or NOP DESELECT or NOP DESELECT or NOP AUTO REFRESH See Table 8 on page 41 Actionn Maintain Power-Down Maintain Self Refresh Exit Power-Down Exit Self Refresh Precharge Power-Down Entry Active Power-Down Entry Self Refresh Entry Notes
7
H
H
Notes: 1. CKEn is the logic state of CKE at clock edge n; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the DDR SDRAM immediately prior to clock edge n. 3. COMMANDn is the command registered at clock edge n, and ACTIONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. 5. CKE must not drop LOW during a column access. For a READ, this means CKE must stay HIGH until after the read postamble time; for a WRITE, CKE must stay HIGH until the write recovery time (tWR) has been met. 6. Once initialized, including during self refresh mode, VREF must be powered with in the specified range. 7. Upon exit of the self refresh mode the DLL is automatically enabled. A minimum of 200 clock cycles with CKE HIGH is needed before applying a READ command for the DLL to lock. DESELECT or NOP commands should be issued on any clock edges occurring during the tXSNR period.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Table 8:
Current State Any Idle
Truth Table - Current State Bank n - Command to Bank n
Notes: 1-6; notes appear below and on next page CS# H L L L L L L L L L L L L L L RAS# CAS# X H L L L H H L H H L H H H L X H H L L L L H L L H H L L H WE# X H H H L H L L H L L L H L L Command/Action DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) ACTIVE (select and activate row) AUTO REFRESH LOAD MODE REGISTER READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE (deactivate row in bank or banks) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE (truncate READ burst, start PRECHARGE) BURST TERMINATE READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE (truncate WRITE burst, start PRECHARGE) 7 7 10 10 8 10 10, 12 8 9 10, 11 10 8, 11 Notes
Row Active Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled)
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Table 7 on page 40) and after tXSNR has been met (if the previous state was self refresh). 2. This table is bank-specific, except where noted (i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and Table 8, Truth Table - Current State Bank n - Command to Bank n, on page 41 and according to Table 9, Truth Table - Current State Bank n Command to Bank m, on page 43. Precharging: Starts with registration of a PRECHARGE command and ends when t RP is met. Once tRP is met, the bank will be in the idle state. Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met, the bank will be in the "row active" state. Read w/Auto-Precharge Enabled: Starts with registration of a READ command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. Write w/Auto-Precharge Enabled: Starts with registration of a WRITE command with auto precharge enabled and ends when tRP has been met. Once tRP is met, the bank will be in the idle state. 5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be applied on each positive clock edge during these states.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Refreshing: Starts with registration of an AUTO REFRESH command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM will be in the all banks idle state. Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM will be in the all banks idle state. Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is met, all banks will be in the idle state. All states and sequences not shown are illegal or reserved. Not bank-specific; requires that all banks are idle, and bursts are not in progress. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging. Not bank-specific; BURST TERMINATE affects the most recent READ burst, regardless of bank. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. Requires appropriate DM masking. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
6. 7. 8. 9. 10. 11. 12.
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128Mb: x4, x8, x16 DDR SDRAM Operations
Table 9: Truth Table - Current State Bank n - Command to Bank m
Notes: 1-6; notes appear below and on next page Current State Any Idle Row Activating, Active, or Precharging Read (AutoPrecharge Disabled) Write (AutoPrecharge Disabled) Read (With AutoPrecharge) Write (With AutoPrecharge) CS# H L X L L L L L L L L L L L L L L L L L L L L RAS# X H X L H H L L H H L L H H L L H H L L H H L CAS# X H X H L L H H L L H H L L H H L L H H L L H WE# X H X H H L L H H L L H H L L H H L L H H L L Command/Action DESELECT (NOP/continue previous operation) NO OPERATION (NOP/continue previous operation) Any Command Otherwise Allowed to Bank m ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start new READ burst) WRITE (select column and start WRITE burst) PRECHARGE ACTIVE (select and activate row) READ (select column and start READ burst) WRITE (select column and start new WRITE burst) PRECHARGE Notes
7 7
7 7, 9
7, 8 7
7, 3a 7, 9, 3a
7, 3a 7, 3a
Notes: 1. This table applies when CKEn-1 was HIGH and CKEn is HIGH (see Truth Table 2) and after tXSNR has been met (if the previous state was self refresh). 2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3. Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated Read with auto precharge enabled: see following text - 3a Write with auto precharge enabled: see following text - 3a a. The READ with auto precharge enabled or WRITE with auto precharge enabled states can each be broken into two parts: the access period and the precharge period. For READ with auto precharge, the precharge period is defined as if the same burst was executed with auto precharge disabled and then followed with the earliest possible PRECHARGE command that still accesses all of the data in the burst. For WRITE with auto precharge, the precharge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period starts with registration of the command and ends where the precharge period (or tRP) begins. This device supports concurrent auto precharge such that when a READ with auto pre-
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128Mb: x4, x8, x16 DDR SDRAM Operations
charge is enabled or a WRITE with auto precharge is enabled any command to other banks is allowed, as long as that command does not interrupt the read or write data transfer already in process. In either case, all other related limitations apply (e.g., contention between read data and write data must be avoided). b.The minimum delay from a READ or WRITE command with auto precharge enabled, to a command to a different bank is summarized below. CLRU = 25 Latency (CL) rounded up to the next integer BL = Bust Length Minimum Delay (with Concurrent Auto Precharge) [1 + (BL/2)] x tCK + tWTR (BL/2) x tCK 1 tCK 1 tCK (BL/2) x tCK [CLRU + (BL/2)] x tCK 1 tCK 1 tCK
From Command WRITE w/AP
To Command READ or READ w/AP WRITE or WRITE w/AP PRECHARGE ACTIVE READ or READ w/AP WRITE or WRITE w/AP PRECHARGE ACTIVE
READ w/AP
4. AUTO REFRESH and LOAD MODE REGISTER commands may only be issued when all banks are idle. 5. A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. All states and sequences not shown are illegal or reserved. 7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. Requires appropriate DM masking. 9. A WRITE command may be applied after the completion of the READ burst; otherwise, a BURST TERMINATE must be used to end the READ burst prior to asserting a WRITE command.
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128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Electrical Specifications
Table 4: Absolute Maximum Ratings
Voltage VDD Supply Voltage Relative to Vss VDDQ Supply Voltage Relative to VSS VREF and Inputs Voltage Relative to VSS I/O Pins Voltage Relative to VSS Operating Temperature, TA (Ambient, Commercial) Operating Temperature, TA (Ambient, Industrial) Storage Temperature (Plastic) Short Circuit Output Current Note: MIN MAX Units V V V V C C C mA
-1 +3.6 -1 +3.6 -1 +3.6 -0.5 to VDDQ +0.5 0 +70 -40 -55 +85 +150 50
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Table 5:
DC Electrical Characteristics and Operating Conditions (-6, -6T, -75E, -75Z, -75)
0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 16, notes appear on page 62-67
Parameter/Condition Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF Pin 0V VIN 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: Full drive option - x4, x8, x16 High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) OUTPUT LEVELS: Reduced drive option - x16 only High Current (VOUT = VDDQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
Symbol VDD VDDQ VREF VTT VIH(DC) VIL(DC)
MIN 2.3 2.3 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -2
MAX 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 2
Units V V V V V V A
Notes 36, 41 36, 41, 44 6, 44 7, 44 28 28
II
IOZ
-5 -16.8
5 -
A mA 37, 39
IOH
IOL IOHR
16.8 -9
- -
mA mA 38, 39
IOLR
9
-
mA
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128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 6: DC Electrical Characteristics and Operating Conditions (-5B DDR400)
0C TA +70C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V Notes: 1-5, 16, and 53; Notes appear on page 62-67 Parameter/Condition Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V VIN VDD, VREF Pin 0V VIN 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V VOUT VDDQ) OUTPUT LEVELS: Full drive option - x4, x8, x16 High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) OUTPUT LEVELS: Reduced drive option - x16 only High Current (VOUT = VDDQ - 0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF, maximum VTT) Symbol VDD VDDQ VREF VTT VIH(DC) VIL(DC) IL MIN 2.5 2.5 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -2 MAX 2.7 2.7 0.51 x VDDQ VREF + 0.04 VDD + 0.3 VREF - 0.15 2 Units V V V V V V A Notes 36, 41, 52 36, 41, 44, 52 6, 44 7, 44 28 28
IOZ IOH
-5 -16.8
5 -
A mA 37, 39
IOL IOHR
16.8 -9
- -
mA mA 38, 39
IOLR
9
-
mA
Table 7:
AC Input Operating Conditions
0C TA +70C; VDDQ = VDD = +2.5V 0.2V (VDDQ = VDD = +2.6V 0.1V for DDR400) Notes: 1-5, 16, notes appear on page 62-67
Parameter/Condition Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage
Symbol VIH(AC) VIL(AC) VREF(AC)
MIN VREF + 0.310 - 0.49 x VDDQ
MAX - VREF - 0.310 0.51 x VDDQ
Units V V V
Notes 14, 28, 40 14, 28, 40 6
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128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Figure 31: Input Voltage Waveform
VDDQ (2.3V minimum)
1 VOH(MIN) (1.670V for SSTL2 termination) System Noise Margin (Power/Ground, Crosstalk, Signal Integrity Attenuation) 1.560V VIHAC
1.400V
VIHDC
1.300V 1.275V 1.250V 1.225V 1.200V
VREF +AC Noise VREF +DC Error VREF -DC Error VREF -AC Noise
1.100V
VILDC
0.940V VINAC - Provides margin between VOL (MAX) and VILAC VOL (MAX) (0.83V2 for SSTL2 termination)
VILAC
Receiver
Transmitter
VSSQ
NOTE: 1. VOH (MIN) with test load is 1.927V 2. VOL (MAX) with test load is 0.373V 3. For non-DDR400 devices, numbers in diagram reflect nomimal values utilizing circuit below.
VTT 25 25 Reference Point
Table 8:
Clock Input Operating Conditions
0C TA +70C; VDDQ = VDD = +2.5V 0.2V (VDDQ = VDD = +2.6V 0.1V for DDR400) Notes: 1-5, 15, 16, 30; notes appear on page 62-67
Parameter/Condition Clock Input Mid-Point Voltage; CK and CK# Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK#
Symbol
MIN
MAX
Units V V V V V
Notes 6, 9 6 6, 8 8 9
VMP(DC) VIN(DC)
VID(DC) VID(AC) VIX(AC)
1.15 1.35 -0.3 VDDQ + 0.3 0.36 VDDQ + 0.6 0.7 VDDQ + 0.6 0.5 x VDDQ - 0.2 0.5 x VDDQ + 0.2
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Figure 32:
2.80V
CK#
SSTL_2 Clock Input
Maximum Clock Level
5
1.45V 1.25V 1.05V
X
VMP(DC)
1
VIX(AC)
2
VID(DC) VID(AC)
3
4
X
CK
- 0.30V
Minimum Clock Level
5
Notes: 1. 2. 3. 4. 5. 6. 7.
This provides a minimum of 1.15V to a maximum of 1.35V, and is always half of VDDQ. CK and CK# must cross in this region. CK and CK# must meet at least VID(DC) MIN when static and is centered around VMP (DC) CK and CK# must have a minimum 700mv peak to peak swing. CK or CK# may not be more positive than VDDQ + 0.3V or more negative than Vss - 0.3V. For AC operation, all DC clock requirements must also be satisfied. Numbers in diagram reflect nominal values, for non-DDR400 devices.
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 9:
Parameter Delta Input/Output Capacitance: DQ0-DQ3 (x4), DQ0-DQ7 (x8) Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE
Capacitance (x4, x8 TSOP)
Note: 13; notes appear on page 62-67 Symbol MIN - - - 4.0 2.0 2.0 2.0 MAX 0.50 0.50 0.25 5.0 3.0 3.0 3.0 Units pF pF pF pF pF pF pF Notes 24 29 29
DCIO DCI1 DCI2 CIO
CI1 CI2
CI3
Table 10:
Parameter
Capacitance (x16 TSOP)
Note: 13; notes appear on page 62-67 Symbol MIN - - - - 4.0 2.0 2.0 2.0 MAX 0.50 0.50 0.50 0.25 5.0 3.0 3.0 3.0 Units pF pF pF pF pF pF pF pF Notes 24 24 29 29
Delta Input/Output Capacitance: DQ0-DQ7, LDQS, LDM Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQ, LDQS, UDQS, LDM, UDM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE
DCIOL DCIOU DCI1 DCI2 CIO CI1 CI2 CI3
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 11: IDD Specifications and Conditions (x4, x8; -5B)
0C TA +70C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V Notes: 1-5, 10, 12, 14, 46; notes appear on page 62-67; See also Table 17, Idd Test Cycle Times, on page 56 MAX Parameter/Condition
t
Symbol IDD0
-5B 115
Units mA
Notes 22, 47
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRC (MIN) AUTO REFRESH BURST CURRENT: tREFC = 15.6s SELF REFRESH CURRENT: CKE 0.2V Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during ACTIVE, READ, or WRITE commands
OPERATING CURRENT: One bank; Active-Precharge; RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge;
IDD1
135
mA
22, 47
IDD2P IDD2F
3 50
mA mA
23, 32 50
IDD3P IDD3N
30 50
mA mA
23, 32 22
IDD4R
165
mA
22, 47
IDD4W
160
mA
22
IDD5 IDD5A IDD6 IDD6A IDD7
240 6 4 1.3 355
mA mA mA mA mA
49 27, 49 11 11 22, 48
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 12: IDD Specifications and Conditions (x4, x8; -6T/-75E)
0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 10, 12, 14, 46; notes appear on page 62-67; See also Table 17, Idd Test Cycle Times, on page 56 MAX Parameter/Condition OPERATING CURRENT: One bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Symbol IDD0 -6T 125 -75E 110 Units mA Notes 22, 47
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
IDD1
135
120
mA
22, 47
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRC (MIN) AUTO REFRESH BURST CURRENT: tREFC = 15.6s SELF REFRESH CURRENT: CKE 0.2V Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during ACTIVE, READ, or WRITE commands
IDD2P IDD2F
3 45
3 45
mA mA
23, 32 50
IDD3P IDD3N
25 50
25 50
mA mA
23, 32 22
IDD4R
145
130
mA
22, 47
IDD4W
140
125
mA
22
IDD5 IDD5A IDD6 IDD6A IDD7
265 5 3 1.3 355
220 5 3 1.3 330
mA mA mA mA mA
49 27, 49 11 11 22, 48
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 13: IDD Specifications and Conditions (x4, x8; -75Z/-75)
0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 10, 12, 14, 46; notes appear on page 62-67; See also Table 17, Idd Test Cycle Times, on page 56 MAX Parameter/Condition OPERATING CURRENT: One bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Symbol IDD0 -75Z/-75 105 Units mA Notes 22, 47
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
IDD1
120
mA
22, 47
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC =tRC (MIN) AUTO REFRESH BURST CURRENT: tREFC = 15.6s SELF REFRESH CURRENT: CKE 0.2V Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during ACTIVE, READ, or WRITE commands
IDD2P IDD2F
3 40
mA mA
23, 32 50
IDD3P IDD3N
25 45
mA mA
23, 32 22
IDD4R
130
mA
22, 47
IDD4W
125
mA
22
IDD5 IDD5A IDD6 IDD6A IDD7
220 5 2 1.3 325
mA mA mA mA mA
49 27, 49 11 11 22, 48
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 14: IDD Specifications and Conditions (x16; -5B)
0C TA +70C; VDDQ = +2.6V 0.1V, VDD = +2.6V 0.1V Notes: 1-5, 10, 12, 14, 46; notes appear on page 62-67; See also Table 17, Idd Test Cycle Times, on page 56 MAX Parameter/Condition OPERATING CURRENT: One bank; Active-Precharge; RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRC (MIN) AUTO REFRESH BURST CURRENT: tREFC = 15.6s SELF REFRESH CURRENT: CKE 0.2V Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during ACTIVE, READ, or WRITE commands
t
Symbol IDD0
-5B 125
Units mA
Notes 22, 47
IDD1
135
mA
22, 47
IDD2P IDD2F
3 50
mA mA
23, 32 50
IDD3P IDD3N
30 50
mA mA
23, 32 22
IDD4R
185
mA
22, 47
IDD4W
180
mA
22
IDD5 IDD5A IDD6 IDD6A IDD7
265 10 4 1.3 385
mA mA mA mA mA
49 27, 49 11 11 22, 48
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 15: IDD Specifications and Conditions (x16; -6T/-75E)
0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 10, 12, 14, 46; notes appear on page 62-67; See also Table 17, Idd Test Cycle Times, on page 56 MAX Parameter/Condition OPERATING CURRENT: One bank; Active-Precharge; RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRC (MIN) AUTO REFRESH BURST CURRENT: tREFC = 15.6s SELF REFRESH CURRENT: CKE 0.2V Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during ACTIVE, READ, or WRITE commands
t
Symbol IDD0
-6T 125
-75E 115
Units mA
Notes 22, 47
IDD1
135
135
mA
22, 47
IDD2P
3
3
mA
23, 32
IDD2F
45
45
mA
50
IDD3P IDD3N
25 50
25 50
mA mA
23, 32 22
IDD4R
165
140
mA
22, 47
IDD4W
160
140
mA
22
IDD5 IDD5A IDD6 IDD6A IDD7
265 5 3 1.3 385
250 5 3 1.3 375
mA mA mA mA mA
49 27, 49 11 11 22, 48
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 16: IDD Specifications and Conditions (x16; -75Z/-75)
0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 1-5, 10, 12, 14, 46; notes appear on page 62-67; See also Table 17, Idd Test Cycle Times, on page 56 MAX Parameter/Condition OPERATING CURRENT: One bank; Active-Precharge; = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One bank; Active-Read-Precharge;
tRC
Symbol IDD0
-75Z/-75 110
Units mA
Notes 22, 47
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle
IDD1
125
mA
22, 47
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle; t CK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank active; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRC (MIN) AUTO REFRESH BURST CURRENT: tREFC = 15.6s SELF REFRESH CURRENT: CKE 0.2V Standard Low Power (L) OPERATING CURRENT: Four bank interleaving READs (Burst = 4) with auto precharge, tRC = minimum tRC allowed; tCK = tCK (MIN); Address and control inputs change only during ACTIVE, READ, or WRITE commands
IDD2P IDD2F
3 40
mA mA
23, 32 50
IDD3P IDD3N
25 45
mA mA
23, 32 22
IDD4R
140
mA
22, 47
IDD4W
140
mA
22
IDD5 IDD5A IDD6 IDD6A IDD7
250 5 2 1.3 375
mA mA mA mA mA
49 27, 49 11 11 22, 48
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 17: IDD Test Cycle Times
Values reflect number of clock cycles for each test IDD Test IDD0 Speed Grade -75/75Z -75E -6T -5B -75 -75Z -75E -6T -5B -75 -75Z -75E -6T -5B -75 -75Z -75E -6T -5B -75/75Z -75E -6T -5B -75/75Z -75E -6T -5B -75 -75Z -75E -6T -5B Clock Cycle Time 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 6ns 5ns 7.5ns 7.5ns 7.5ns 6ns 5ns
t
RRD NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 2/4 2/4 2 2/4 2/4
t
RCD NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 3 3 3 3 3
t
RAS 6 6 7 8 6 6 6 7 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA
t
RP
t
RC
t
RFC NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 10 9 12 14 10 9 12 14 NA NA NA NA NA
t
REFI
CL NA NA NA NA 2.5 2 2 2.5 3 2.5 2 2 2.5 3 NA NA NA NA NA NA NA NA NA NA NA NA NA 2.5 2 2 2.5 3
IDD1
IDD4R
IDD4W
IDD5
IDD5A
IDD7
3 2 3 3 3 3 2 3 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 3 3 2 3 3
9 8 10 11 9 9 8 10 NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 10 10 8 10 11
NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 10 9 12 14 1,030 1,031 1,288 1,564 NA NA NA NA NA
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Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 18: Electrical Characteristics and Recommended AC Operating Conditions (-5B)
Notes: 1-5, 14-17, 33; notes appear on page 62-67; 0C TA +70C; VDD = VDDQ = +2.6V 0.1V AC Characteristics Parameter
Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time
-5B Symbol
tAC tCH
MIN
-0.70 0.45 0.45 5 6 7.5 0.40 0.40 1.75 -0.6 0.35 0.35 0.72 0.2 0.2 t CH,tCL -0.7 0.6 0.6 0.6 0.6 2.2 10 t HP -tQHS
MAX
+0.70 0.55 0.55 7.5 13 13
Units
ns tCK t CK ns ns ns ns ns ns ns t CK tCK ns t CK t CK t CK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK tCK ns t CK ns t CK ns tCK ns s s ns ns
Notes
30 30 51 45, 51 45, 51 26, 31 26, 31 31
CL = 3 CL = 2.5 CL = 2
DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command
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CL CK (3) t CK (2.5) t CK (2) tDH t DS t DIPW t DQSCK t DQSH tDQSL tDQSQ t DQSS t DSS t DSH t HP tHZ tLZ t IHF t ISF t IHS t ISS tIPW tMRD t QH t QHS t RAS t RAP tRC t RFC t RCD t RP t RPRE tRPST tRRD t WPRE t WPRES t WPST t WR tWTR N/A t REFC t REFI t VTD t XSNR
t
t
+0.6
0.4 1.28
25, 26
+0.7
34 18, 42 18, 42
14 14
25, 26 35
40 15 55 70 15 15 0.9 1.1 0.4 0.6 10 0.25 0 0.4 0.6 15 2 tQH - tDQSQ 140.6 15.6 0 70
0.5 70,000
49
43 43
20, 21 19
25 23 23
57
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128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 18: Electrical Characteristics and Recommended AC Operating Conditions (-5B) (Continued)
Notes: 1-5, 14-17, 33; notes appear on page 62-67; 0C TA +70C; VDD = VDDQ = +2.6V 0.1V AC Characteristics Parameter
Exit SELF REFRESH to READ command
-5B Symbol
tXSRD
MIN
200
MAX
Units
tCK
Notes
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128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 19: Electrical Characteristics and Recommended AC Operating Conditions (-6T/-75E)
Notes: 1-5, 14-17, 33; notes appear on page 62-67; 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V AC Characteristics Parameter
Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time
-6T Symbol
AC t CH tCL tCK (2.5) t CK (2) t DH t DS tDIPW tDQSCK t DQSH t DQSL t DQSQ t DQSS tDSS tDSH t HP t HZ t LZ t IHF tIS F tIH S t ISS t IPW t MRD t QH QHS RAS t RAP tRC tRFC t RCD t RP t RPRE t RPST tRRD tWPRE t WPRES t WPST t WR t WTR N/A tREFC t REFI t VTD t XSNR t XSRD
t t t
-75E MAX
+0.70 0.55 0.55 13 13
MIN
-0.70 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.6 0.35 0.35 0.75 0.2 0.2 t CH,tCL -0.7 0.75 0.75 0.8 0.8 2.2 12 t HP -tQHS
MIN
-0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 0.75 0.2 0.2 t CH,tCL -0.75 .90 .90 1 1 2.2 15 t HP -tQHS
MAX
+0.75 0.55 0.55 13 13
Units
ns t CK tCK ns ns ns ns ns ns t CK t CK ns t CK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK t CK ns tCK ns t CK ns t CK ns s s ns ns t CK
Notes
30 30 45, 51 45, 51 26, 31 26, 31 31
CL = 2.5 CL = 2
DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
+0.6
+0.75
0.45 1.25
0.5 1.25
25, 26
+0.7
+0.75
34 18, 42 18, 42
14 14
25, 26
0.55 42 70,000 15 60 72 15 15 0.9 1.1 0.4 0.6 12 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 15.6 0 75 200
0.75 40 120,000 15 60 75 15 15 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 15.6 0 75 200
35, 53
49
43 43
20, 21 19
25 23 23
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Table 20: Electrical Characteristics and Recommended AC Operating Conditions (-75Z/-75)
Notes: 1-5, 14-17, 33; notes appear on page 62-67; 0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V AC Characteristics Parameter
Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time
-75Z Symbol
AC t CH tCL tCK (2.5) t CK (2) t DH t DS tDIPW tDQSCK t DQSH t DQSL t DQSQ t DQSS tDSS tDSH t HP t HZ t LZ t IHF tIS F tIH S t ISS t IPW t MRD t QH QHS RAS t RAP tRC tRFC t RCD t RP t RPRE t RPST tRRD tWPRE t WPRES t WPST t WR t WTR N/A tREFC t REFI t VTD t XSNR t XSRD
t t t
-75 MAX
+0.75 0.55 0.55 13 13
MIN
-0.75 0.45 0.45 7.5 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 0.75 0.2 0.2 t CH,tCL -0.75 .90 .90 1 1 2.2 15 t HP -tQHS
MIN
-0.75 0.45 0.45 7.5 10 0.5 0.5 1.75 -0.75 0.35 0.35 0.75 0.2 0.2 t CH,tCL -0.75 .90 .90 1 1 2.2 15 t HP -tQHS
MAX
+0.75 0.55 0.55 13 13
Units
ns t CK tCK ns ns ns ns ns ns t CK t CK ns t CK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK t CK ns tCK ns t CK ns t CK ns s s ns ns t CK
Notes
30 30 45, 51 45, 51 26, 31 26, 31 31
CL = 2.5 CL = 2
DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data Hold Skew Factor ACTIVE to PRECHARGE command ACTIVE to READ with auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window (DVW) REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command
+0.75
+0.75
0.5 1.25
0.5 1.25
25, 26
+0.75
+0.75
34 18, 42 18, 42
14 14
25, 26
0.75 40 120,000 20 65 75 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 15.6 0 75 200
0.75 40 120,000 20 65 75 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 15.6 0 75 200
35
49
43 43
20, 21 19
25 23 23
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128Mb: x4, x8, x16 DDR SDRAM Electrical Specifications
Table 21:
Input Slew Rate Derating Values for Addresses and Commands
0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 14; notes appear on page 62-67 Speed -75/-75Z/-75E -75/-75Z/-75E -75/-75Z/-75E Slew Rate 0.5 V/ns Slew Rate < 1.0 V/ns 0.4 V/ns Slew Rate < 0.5 V/ns 0.3 V/ns Slew Rate < 0.4 V/ns
t
IS
t
IH 1 1 1
Units ns ns ns
1.00 1.05 1.15
Table 22:
Input Slew Rate Derating Values for DQ, DQS, and DM
0C TA +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V Notes: 31; notes appear on page 62-67 Speed -75/-75Z/-75E -75/-75Z/-75E -75/-75Z/-75E Slew Rate 0.5 V/ns Slew Rate < 1.0 V/ns 0.4 V/ns Slew Rate < 0.5 V/ns 0.3 V/ns Slew Rate < 0.4 V/ns
tDS tDH
Units ns ns ns
0.50 0.55 0.60
0.50 0.55 0.60
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128Mb: x4, x8, x16 DDR SDRAM Notes
Notes
1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs (except for IDD measurements) measured with equivalent load:
VTT 50 Reference Point 30pF
Output (VOUT)
4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL (AC) and VIH (AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 9. The value of VIX and VMP are expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle times at CL = 3 for -5B, CL = 2.5 for -6/-6T and -75, and CL = 2 for -75E/-75Z speeds with the outputs open. 11. Enables on-chip refresh and address counters. 12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. This parameter is sampled. VDD = +2.5V0.2V, VDDQ = +2.5V0.2V, VREF = VSS, f = 100MHz, TA = 25C VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. For slew rates less than 1V/ns and greater than or equal to 0.5Vns. If slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from 500mV/ns, while tIH has 0pF is unaffected. If slew rate exceeds 4.5V/ns, functionality is uncertain. For -5B, -6, and -6T speed grades, slew rates must be greater than or equal 0.5V/ns.
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128Mb: x4, x8, x16 DDR SDRAM Notes
15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Once initialized, including self refresh mode, VREF must be powered within specified range. Exception: during the period before VREF stabilizes, CKE 0.3 x VDDQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. Transitions occur in the same access time windows as data valid transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (tHZ) or begins driving (tLZ). 19. The intent of the Don't Care state after completion of the postamble is the DQS-driven signal should either be HIGH, LOW, or High-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions HIGH (above VIH (DC) [MIN]) then it must not transition LOW (below VIH (DC) prior to tDQSH (MIN). 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 22. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that
meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS.
23. The refresh period is 64ms. This equates to an average refresh rate of 15.625s. However, an AUTO REFRESH command must be asserted at least once every 140.6s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given device. 25. The data valid window is derived by achieving other specifications - tHP (tCK/2), t DQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct proportion to the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, because functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided in Figure 33 for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-DQ7; and UDQS with DQ8-DQ15. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC).
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128Mb: x4, x8, x16 DDR SDRAM Notes
29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CK and CK# input slew rate must be 1V/ns ( 2V/ns if measured differentially). 31. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. For -6, -6T, and -5B speed grades, slew rate must be 0.5V/ns. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VDD must not vary more than 4 percent if CKE is not active while any bank is active. 33. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP (MIN) is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 36. Any positive glitch must be less than 1/3 of the clock cycle and not more than +400mV or 2.9V (+300mV or 2.9V maximum for -5B), whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V, (2.4V for -5B) whichever is more positive. The average cannot be below the +2.5V (2.6V for -5B) minimum. 37. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 34
Figure 33:
Derating Data Valid Window (tQH - tDQSQ)
Examples are for speed grades through -75
3.8 3.750 3.6 3.400 3.4 3.700
3.650
3.600 3.550 3.500 3.450 3.400 3.200 3.150 3.100 3.050 3.000 2.950 2.900 3.350 3.300 3.250
3.350
3.300 3.250
3.2
---- -75 @ tCK = 10ns
3.0
ns
---- -8 @ tCK = 10ns ---- -75 @ tCK = 7.5ns ---- -8 @ tCK = 8ns
2.8
2.6
2.500
2.463
2.425
2.388
2.4
2.350
2.313
2.275
2.238
2.200
2.2
2.163
2.125
2.0
1.8 50/50 49.5/50.5 4 9/51 48.5/52.5 48/52 47.5/53.5 Clock Du ty C y c le 47/53 46.5/54.5 46/54 45.5/55.5 45/55
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128Mb: x4, x8, x16 DDR SDRAM Notes
b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 34. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 35. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 35. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. f ) The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. Figure 34: Full Drive Pull-Down Characteristics
160 140 120 100
IOUT (mA)
80 60 40 20 0 0.0 0.5 1.0 VOUT (V) 1.5 2.0 2.5
Figure 35:
Full Drive Pull-Up Characteristics
0 -20 -40 -60
IOUT (m A)
-80 -100 -120 -140 -160 -180 -200 0.0 0.5 1.0 1.5 2.0 2.5 VDDQ - V OUT (V )
38. Reduced Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 36. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 36.
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128Mb: x4, x8, x16 DDR SDRAM Notes
c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 37. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 37. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4 for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity 10 percent, for device drain-to-source voltages from 0.1V to 1.0V. Figure 36: Reduced Drive Pull-Down Characteristics
80 70 60 50
IOUT (mA)
40 30 20 10 0 0.0 0.5 1.0 VOUT (V) 1.5 2.
Figure 37:
Reduced Drive Pull-Up Characteristics
0
-10
-20
-30
IOUT (mA)
-40
-50
-60
-70
-80 0.0 0.5 1.0 VDDQ - VOUT (V) 1.5 2.0 2.5
39. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. 40. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. VDD and VDDQ must track each other. 42. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
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128Mb: x4, x8, x16 DDR SDRAM Notes
43. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). 44. During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42 of series resistance is used between the VTT supply and the input pin. 45. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. 46. When an input signal is HIGH or LOW, it is defined as a steady state logic high or logic low. 47. Random addressing, 50 percent of data changing at every transfer. 48. Random addressing, 100 percent of data changing at every transfer. 49. CKE must be active (HIGH) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tRFC has been satisfied. 50. IDD2N specifies the DQ, DQS and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is "worst case." 51. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset followed by 200 clock cycles before any READ command. 52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20 MHz. Any noise above 20 MHz at the DRAM generated from any source other than that of the DRAM itself may not exceed the DC voltage range of 2.6V100mV. 53. The -6/-6T speed grades will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency.
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128Mb: x4, x8, x16 DDR SDRAM Drive Characteristics
Drive Characteristics
Table 23: Normal Output Drive Characteristics
Pull-Down Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Nominal LOW 6.0 12.2 18.1 24.1 29.8 34.6 39.4 43.7 47.5 51.3 54.1 56.2 57.9 59.3 60.1 60.5 61.0 61.5 62.0 62.5 62.8 63.3 63.8 64.1 64.6 64.8 65.0 Note: Nominal HIGH 6.8 13.5 20.1 26.6 33.0 39.1 44.2 49.8 55.2 60.3 65.2 69.9 74.2 78.4 82.3 85.9 89.1 92.2 95.3 97.2 99.1 100.9 101.9 102.8 103.8 104.6 105.4 Minimum 4.6 9.2 13.8 18.4 23.0 27.7 32.2 36.8 39.6 42.6 44.8 46.2 47.1 47.4 47.7 48.0 48.4 48.9 49.1 49.4 49.6 49.8 49.9 50.0 50.2 50.4 50.5 Maximum 9.6 18.2 26.0 33.9 41.8 49.4 56.8 63.2 69.9 76.3 82.5 88.3 93.8 99.1 103.8 108.4 112.1 115.9 119.6 123.3 126.5 129.5 132.4 135.0 137.3 139.2 140.8 Nominal LOW -6.1 -12.2 -18.1 -24.0 -29.8 -34.3 -38.1 -41.1 -43.8 -46.0 -47.8 -49.2 -50.0 -50.5 -50.7 -51.0 -51.1 -51.3 -51.5 -51.6 -51.8 -52.0 -52.2 -52.3 -52.5 -52.7 -52.8 Pull-Up Current (mA) Nominal HIGH -7.6 -14.5 -21.2 -27.7 -34.1 -40.5 -46.9 -53.1 -59.4 -65.5 -71.6 -77.6 -83.6 -89.7 -95.5 -101.3 -107.1 -112.4 -118.7 -124.0 -129.3 -134.6 -139.9 -145.2 -150.5 -155.3 -160.1 Minimum -4.6 -9.2 -13.8 -18.4 -23.0 -27.7 -32.2 -36.0 -38.2 -38.7 -39.0 -39.2 -39.4 -39.6 -39.9 -40.1 -40.2 -40.3 -40.4 -40.5 -40.6 -40.7 -40.8 -40.9 -41.0 -41.1 -41.2 Maximum -10.0 -20.0 -29.8 -38.8 -46.8 -54.4 -61.8 -69.5 -77.3 -85.2 -93.0 -100.6 -108.1 -115.5 -123.0 -130.4 -136.7 -144.2 -150.5 -156.9 -163.2 -169.6 -176.0 -181.3 -187.6 -192.9 -198.2
The above characteristics are specified under best, worst, and nominal process variation/ conditions.
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128Mb: x4, x8, x16 DDR SDRAM Drive Characteristics
Table 24: Reduced Output Drive Characteristics
Pull-Down Current (mA) Voltage (V) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 Nominal LOW 3.4 6.9 10.3 13.6 16.9 19.9 22.3 24.7 26.9 29.0 30.6 31.8 32.8 33.5 34.0 34.3 34.5 34.8 35.1 35.4 35.6 35.8 36.1 36.3 36.5 36.7 36.8 Note: Nominal HIGH 3.8 7.6 11.4 15.1 18.7 22.1 25.0 28.2 31.3 34.1 36.9 39.5 42.0 44.4 46.6 48.6 50.5 52.2 53.9 55.0 56.1 57.1 57.7 58.2 58.7 59.2 59.6 Minimum 2.6 5.2 7.8 10.4 13.0 15.7 18.2 20.8 22.4 24.1 25.4 26.2 26.6 26.8 27.0 27.2 27.4 27.7 27.8 28.0 28.1 28.2 28.3 28.3 28.4 28.5 28.6 Maximum 5.0 9.9 14.6 19.2 23.6 28.0 32.2 35.8 39.5 43.2 46.7 50.0 53.1 56.1 58.7 61.4 63.5 65.6 67.7 69.8 71.6 73.3 74.9 76.4 77.7 78.8 79.7 Nominal LOW -3.5 -6.9 -10.3 -13.6 -16.9 -19.4 -21.5 -23.3 -24.8 -26.0 -27.1 -27.8 -28.3 -28.6 -28.7 -28.9 -28.9 -29.0 -29.2 -29.2 -29.3 -29.5 -29.5 -29.6 -29.7 -29.8 -29.9 Pull-Up Current (mA) Nominal HIGH -4.3 -7.8 -12.0 -15.7 -19.3 -22.9 -26.5 -30.1 -33.6 -37.1 -40.3 -43.1 -45.8 -48.4 -50.7 -52.9 -55.0 -56.8 -58.7 -60.0 -61.2 -62.4 -63.1 -63.8 -64.4 -65.1 -65.8 Minimum -2.6 -5.2 -7.8 -10.4 -13.0 -15.7 -18.2 -20.4 -21.6 -21.9 -22.1 -22.2 -22.3 -22.4 -22.6 -22.7 -22.7 -22.8 -22.9 -22.9 -23.0 -23.0 -23.1 -23.2 -23.2 -23.3 -23.3 Maximum -5.0 -9.9 -14.6 -19.2 -23.6 -28.0 -32.2 -35.8 -39.5 -43.2 -46.7 -50.0 -53.1 -56.1 -58.7 -61.4 -63.5 -65.6 -67.7 -69.8 -71.6 -73.3 -74.9 -76.4 -77.7 -78.8 -79.7
The above characteristics are specified under best, worst, and nominal process variation/ conditions.
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128Mb: x4, x8, x16 DDR SDRAM Data Timing
Data Timing
Figure 38: x4, x8 Data Output Timing - tDQSQ, tQH, and Data Valid Window
T1 T2 T2n T3 T3n T4
CK# CK
tHP5 tHP5 tDQSQ3 tHP5 tDQSQ3 tHP5 tHP5 tDQSQ3 tHP5 tDQSQ3
DQS1
DQ (Last data valid) DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ (First data no longer valid)
tQH4 tQH4 tQH4 tQH4
DQ (Last data valid) DQ (First data no longer valid)
T2 T2
T2n T2n
T3 T3
T3n T3n
All DQ and DQS, collectively6 Earliest signal transition Latest signal transition
T2
T2n
T3
T3n
Data Valid window
Data Valid window
Data Valid window
Data Valid window
Notes: 1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are an "early DQS," at T3 is a "nominal DQS," and at T3n is a "late DQS." 2. For a x4, only two DQ apply. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition. 4. tQH is derived from tHP: tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 6. The data valid window is derived for each DQS transitions and is defined as tQH - tDQSQ.
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128Mb: x4, x8, x16 DDR SDRAM Data Timing
Figure 39: x16 Data Output Timing - tDQSQ, tQH, and Data Valid Window
CK# CK
T1 T2 T2n T3 T3n T4
tHP5
tHP5 tDQSQ3
tHP5
tHP5 tDQSQ3
tHP5 tDQSQ3
tHP5 tDQSQ3
LDQS1 DQ (Last data valid)2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ2 DQ (First data no longer valid)2
tQH4 tQH4 tQH4 tQH4
Lower Byte
DQ (Last data valid)2 DQ (First data no longer valid)2 DQ0 - DQ7 and LDQS, collectively6
T2 T2 T2
T2n T2n T2n
T3 T3 T3
T3n T3n T3n
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
Data Valid window
tDQSQ3
UDQS1 DQ (Last data valid)7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ7 DQ (First data no longer valid)7
tQH4 tQH4 tQH4 tQH4
Upper Byte
DQ (Last data valid)7 DQ (First data no longer valid)7 DQ8 - DQ15 and UDQS, collectively6
T2 T2 T2 Data Valid window
T2n T2n T2n Data Valid window
T3 T3 T3 Data Valid window
T3n T3n T3n Data Valid window
Notes: 1. DQ transitioning after DQS transition define tDQSQ window. LDQS defines the lower byte and UDQS defines the upper byte. 2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7. 3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with the last valid DQ transition. 4. tQH is derived from tHP: tQH = tHP - tQHS. 5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active. 6. The data valid window is derived for each DQS transition and is tQH - tDQSQ. 7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.
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128Mb: x4, x8, x16 DDR SDRAM Data Timing
Figure 40: Data Output Timing - tAC and tDQSCK
T07 CK# CK tLZ (MIN) tRPRE DQS, or LDQS/UDQS2 DQ (Last data valid) DQ (First data valid) All DQ values, collectively3 tLZ (MIN)
t
T1
T2
T2n
T3
T3n
T4
T4n
T5
T5n
T6
tDQSCK1 (MAX) tDQSCK1 (MIN)
tDQSCK1 (MAX) tHZ(MAX) tDQSCK1 (MIN) tRPST
T2 T2 T2
T2n T2n T2n
T3 T3 T3
T3n T3n T3n
T4 T4 T4
T4n T4n T4n
T5 T5 T5
T5n T5n T5n
tAC4 (MIN)
tAC4 (MAX)
tHZ (MAX)
Notes: 1. DQSCK is the DQS output window relative to CK and is the "long term" component of DQS skew. 2. DQ transitioning after DQS transition define tDQSQ window. 3. All DQ must transition by tDQSQ after DQS transitions, regardless of tAC. 4. tAC is the DQ output window relative to CK, and is the "long term" component of DQ skew. 5. tLZ (MIN) and tAC (MIN) are the first valid signal transition. 6. tHZ (MAX) and tAC (MAX) are the latest valid signal transition. 7. READ command with CL = 2 issued at T0.
Figure 41:
Data Input Timing
T03 CK# CK tDQSS DQS tWPRES tWPRE DQ DM tDS tDH DI b tDQSL tDQSH tWPST tDSH1 tDSS2 tDSH1 tDSS2 T1 T1n T2 T2n T3
TRANSITIONING DATA DON'T CARE
Notes: 1. 2. 3. 4.
t
DSH (MIN) generally occurs during tDQSS (MIN). tDSS (MIN) generally occurs during tDQSS (MAX). WRITE command issued at T0. For x16, LDQS controls the lower byte and UDQS controls the upper byte.
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128Mb: x4, x8, x16 DDR SDRAM Initialization
Initialization
To ensure device operation the DRAM must be initialized as described below: 1. 2. 3. 4. 5. 6. Simultaneously apply power to VDD and VDDQ. Apply VREF and then VTT power. Assert and hold CKE at a LVCMOS logic low. Provide stable CLOCK signals. Wait at least 200s. Bring CKE HIGH and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. Perform a PRECHARGE ALL command. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. Using the LMR command program the extended mode register (E0 = 0 to enable the DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most significant bit). Wait at least tMRD time, only NOPs or DESELECT commands are allowed. Using the LMR command program the mode register to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required between a DLL RESET and any READ command. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. Issue a PRECHARGE ALL command. Wait at least tRP time, only NOPs or DESELECT commands are allowed. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). Wait at least tRFC time, only NOPs or DESELECT commands are allowed. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). Wait at least tRFC time, only NOPs or DESELECT commands are allowed. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as in step 11. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. At this point the DRAM is ready for any valid command. Note 200 clock cycles are required between step 11 (DLL RESET) and any READ command.
7. 8. 9.
10. 11.
12. 13. 14. 15. 16. 17. 18. 19.
20. 21.
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128Mb: x4, x8, x16 DDR SDRAM Initialization
Figure 42: Initialization Flow Diagram
Step 1 VDD and VDDQ Ramp
2
Apply VREF and VTT
3
CKE must be LVCMOS Low
4
Apply stable CLOCKs
5
Wait at least 200us
6
Bring CKE High with a NOP command
7
PRECHARGE ALL
8
Assert NOP or DESELECT for tRP time
9
Configure Extended Mode Register
10
Assert NOP or DESELECT for tMRD time
11
Configure Load Mode Register and reset DLL
12
Assert NOP or DESELECT for tMRD time
13
PRECHARGE ALL
14
Assert NOP or DESELECT for tRP time
15
Issue AUTO REFRESH command
16
Assert NOP or DESELECT commands for tRFC
17
Issue AUTO REFRESH command
18
Assert NOP or DESELECT for tRFC time
19
Optional LMR command to clear DLL bit
20
Assert NOP or DESELECT for tMRD time
21
DRAM is ready for any valid command
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128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Timing Diagrams
Figure 43:
VDD
Initialize and Load Mode Registers
(( )) (( ))
VDDQ VTT1 VREF
tVTD1
(( )) (( ))
T0 CK# CK
(( )) (( ))
T1
(( )) (( ))
Ta0
(( )) (( ))
Tb0
(( )) (( ))
Tc0
(( )) (( ))
Td0
(( )) (( ))
Te0
(( )) (( ))
Tf0
tCH tIS tIH
tCL
CKE
LVCMOS LOW LEVEL
(( ))
(( )) (( ))
(( )) (( ))
(( )) (( ))
(( )) (( ))
(( )) (( ))
(( )) (( ))
tIS COMMAND6
(( )) (( )) (( )) (( ))
tIH
PRE tCK
(( )) (( )) (( )) (( ))
NOP
LMR
(( )) (( )) (( )) (( ))
LMR
(( )) (( )) (( )) (( ))
PRE
(( )) (( )) (( )) (( ))
AR
(( )) (( )) (( )) (( ))
AR
(( )) (( )) (( )) (( ))
ACT5
DM
tIS A0-A9, A11
(( )) (( )) (( )) (( ))
tIH
(( )) (( ))
CODE
CODE
(( )) (( ))
(( )) (( ))
(( )) (( ))
(( )) (( ))
RA
A10
(( )) (( ))
ALL BANKS
tIS
(( )) (( )) (( )) (( ))
tIH
(( )) (( )) (( )) (( ))
CODE
CODE
tIS
tIH
(( )) (( )) (( )) (( ))
ALL BANKS
tIS
tIH
BA0 = L, BA1 = L
tIS
tIH
(( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( ))
RA
BA0, BA1
(( )) (( ))
BA0 = H, BA1 = L
BA
DQS DQ T = 200s
(( )) (( ))
High-Z High-Z
(( )) (( ))
(( )) (( ))
(( )) (( )) tMRD tRP
(( )) (( ))
(( )) (( )) tRFC
(( )) (( )) tRFC5
Power-up: VDD and CK stable
tRP tMRD Load Extended Mode Register
200 cycles of CK3 Load Mode Register2 DON'T CARE
Notes: 1. VTT is not applied directly to the device; however, should be greater than or equal to zero to avoid device latch-up. VDDQ, VTT, and VREF, must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42 ohms of series resistance is used between the VTT supply and the input pin. Once initialized, inclding during self refresh mode, VREF must always be powered within specified range. 2. Reset the DLL with A8 = H while programming the operating parameters. 3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued. 4. The two AUTO REFRESH commands at Td0 and Te0 may be applied following the LOAD MODE REGISTER (LMR) command at Ta0. 5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any bank. If another command is issued, the same operating parmeters previously issued must be used. 6. PRE = PRECHARGE command, LMR = LOAD MODE REGISTER command, AR = AUTO REFRESH command, ACT = ACTIVE command, RA = Row Address, BA = Bank Address.
tVTD
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128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Figure 44: Power-Down Mode
T0 CK# CK
tIS tIH tCK tIS
(( ))
T1
T2
tCH
tCL
(( )) (( ))
Ta0
Ta1
Ta2
tIS
CKE
tIS tIH NOP
COMMAND
VALID2 tIS tIH
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
NOP
VALID
ADDR
VALID
VALID
DQS
DQ
DM
tREFC
Enter 3 Power-Down Mode
Exit Power-Down Mode DON'T CARE
Notes: 1. Once initialized, including during self refresh mode, VREF must always be powered within specified range. 2. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is precharge power-down. If this command is an ACTIVE (or if at least one row is already active), then the power-down mode shown is active power-down. 3. No column accesses are allowed to be in progress at the time power-down is entered.
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128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Figure 45:
CK# CK
tIS tIH
Auto Refresh Mode
T0 T1 T2 T3 T4
(( )) (( )) (( )) (( ))
Ta0
Ta1
CK
tCH VALID
tCL
(( )) (( )) (( )) (( ))
Tb0
Tb1
Tb2
CKE
tIS tIH PRE
VALID
COMMAND1
NOP 2
NOP2
NOP2
AR
(( )) (( )) (( )) (( ))
NOP2, 3
AR 6
(( )) (( )) (( )) (( )) (( )) (( ))
NOP2, 3
NOP2
ACT
A0-A9, A111
ALL BANKS
RA
A101
ONE BANK
(( )) (( ))
RA
tIS
tIH
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
BA0, BA11
Bank(s)4
BA
DQS5
DQ5
DM5
tRP
tRFC
tRFC5
DON'T CARE
Notes: 1. PRE = PRECHARGE, ACT = ACTIVE, AR = AUTO REFRESH, RA = Row Address, BA = Bank Address. 2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be active during clock positive transitions. 3. NOP or COMMAND INHIBIT are the only commands allowed until after tRFC time, CKE must be active during clock positive transitions. 4. "Don't Care" if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all active banks). 5. DM, DQ, and DQS signals are all "Don't Care"/High-Z for operations shown. 6. The second AUTO REFRESH is not required and is only shown as an example of two backto-back AUTO REFRESH commands.
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128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Figure 46:
CK# CK1
tIS tCH tIH tCL tIS
Self Refresh Mode
T0 T11
(( )) (( ))
Ta01
Ta1
Ta2
(( )) (( ))
Tb1
Tb2
tCK t IS
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
Tc1
CKE
tIS tIH AR
(( ))
(( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( ))
(( )) (( )) (( )) (( )) (( )) (( )) (( )) (( ))
COMMAND2
NOP
NOP
NOP
VALID3
VALID
VALID
tIS
tIH
VALID VALID
ADDR
VALID
DQS
(( )) (( )) (( )) (( )) (( )) (( ))
DQ
DM
tRP4
tXSNR5
tXSRD6
Enter Self Refresh Mode7
Exit Self Refresh Mode7
DON'T CARE
Notes: 1. Clock must be stable until after the SELF REFRESH command has been registered. A change in clock frequency is allowed before Ta0, provided it is within the specified tCK limits. Regardless, the clock must be stable before exiting self refresh mode. That is, the clock must be cycling within specifications by Ta0. 2. NOPs are interchangeable with DESELECT commands, AR = AUTO REFRESH command. 3. Auto Refresh is not required at this point, but is highly recommended. 4. Device must be in the all banks idle state prior to entering self refresh mode. 5. tXSNR is required before any non-READ command can be applied. That is only NOP or DESELECT commands are allowed until Tb1. 6. tXSRD (200 cycles of a valid CK and CKE = HIGH) is required before any READ command can be applied. 7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self refresh mode until all rows have been refreshed via the AUTO REFRESH command at the distributed refresh rate, tREFI, or faster. However, the following exception is allowed. Self refresh mode may be re-entered anytime after exiting, if the following conditions are all met: a. The DRAM had been in the self refresh mode for a minimum of 200ms prior to exiting. b.tXSNR and tXSRD are not violated. c.At least two AUTO REFRESH commands are performed during each tREFI interval while the DRAM remains out of self refresh mode. 8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit. 9. Once initialized, inclding during self refresh mode, VREF must always be powered within specified range.
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128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Figure 47:
CK# CK
tIS tIH tCK tCH tCL
Bank Read - Without Auto Precharge
T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8
CKE
tIS tIH ACT tIS tIH Col n RA NOP6 READ2 NOP6 PRE7 NOP6 NOP6 ACT
COMMAND5
NOP6
x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 x8: A11 x16: A9, A11
RA
RA tIS tIH
ALL BANKS
RA
A10
RA tIS tIH
3
ONE BANK
RA
BA0, BA1
Bank x tRCD tRAS7 tRC
Bank x
Bank x4
Bank x
CL = 2
tRP
DM
Case 1: tAC (MIN) and tDQSCK (MIN)
tRPRE
tDQSCK (MIN) tRPST
DQS
tLZ (MIN)
DQ1
tLZ (MIN)
DO n tAC (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
tRPRE
tDQSCK (MAX) tRPST
DQS
DQ1
DO n tAC (MAX) tHZ (MAX)
DON'T CARE
TRANSITIONING DATA
Notes: 1. DOn = data-out from column n; subsequent elements are provided in the programmed order. 2. BL = 4 in the case shown. 3. Disable auto precharge. 4. "Don't Care" if A10 is HIGH at T5. 5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. The PRECHARGE command can only be applied at T5 if tRAS minimum is met. 8. Refer to Figure 38 on page 70, Figure 39 on page 71, and Figure 40 on page 72 for detailed DQS and DQ timing.
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
79
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Figure 48:
CK# CK
tIS tIH tCK tCH tCL
Bank Read - With Auto Precharge
T0 T1 T2 T3 T4 T5 T5n T6 T6n T7 T8
CKE
tIS tIH ACT tIS tIH Col n RA NOP5 READ2,6 NOP5 NOP5 NOP5 NOP5 ACT
COMMAND4
NOP5
x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 x8: A11 x16: A9, A11 A10 IS BA0, BA1
RA
RA 3 RA tIS tIH
RA
RA
IH
Bank x tRCD, tRAP6 tRAS tRC Bank x
Bank x
CL = 2
tRP7
DM
Case 1: tAC (MIN) and tDQSCK (MIN)
tRPRE
tDQSCK (MIN)
tRPST
DQS DQ1
tLZ (MIN) tLZ (MIN) DO n tAC (MIN)
Case 2: tAC (MAX) and tDQSCK (MAX)
tDQSCK (MAX) tRPRE tRPST
DQS DQ1
DO n tAC (MAX) tHZ (MAX)
DON'T CARE
TRANSITIONING DATA
Notes: 1. DOn = data-out from column n; subsequent elements are provided in the programmed order. 2. BL = 4 in the case shown. 3. Enable auto precharge. 4. ACT = ACTIVE, RA = Row Address, BA = Bank Address. 5. NOP commands are shown for ease of illustration; other commands may be valid at these times. 6. The READ command can only be applied at T3 if tRAP is satisfied at T3. 7. tRP starts only after tRAS has been satisfied. 8. Refer to Figure 38 on page 70, Figure 39 on page 71, and Figure 40 on page 72 for detailed DQS and DQ timing.
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
80
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Figure 49:
CK# CK
tIS tIH tCK tCH tCL
Bank Write - Without Auto Precharge
T0 T1 T2 T3 T3n T4 T4n T5 T5n T6 T7 T8
CKE
tIS tIH ACT tIS tIH Col n NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6 PRE
COMMAND5 x4: A0-A9, A11 x8: A0-A9 x16: A0-A8 x8: A11 x16: A9, A11
NOP6
RA
RA tIS tIH
ALL BANKS
A10
RA tIS tIH
3
ONE BANK
BA0, BA1
Bank x tRCD tRAS
Bank x tWR
Bank x4
tRP tDQSS (NOM)
DQS
tWPRES tWPRE
8
tDQSL
tDQSH tWPST
DQ1 DM tDS
DI b
tDH
DON'T CARE
TRANSITIONING DATA
Notes: 1. DIn = data-in. from column n; subsequent elements are provided in the programmed order. 2. BL = 4 in the case shown. 3. Disable auto precharge. 4. "Don't Care" if A10 is HIGH at T8. 5. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. 6. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. See Figure 43, Initialize and Load Mode Registers, on page 75 for detailed DQ timing. 8. Although not requird by the Micron device, JEDEC specifies that DQS be a valid HIGH, LOW or some point on a valid transition on or before this clock edge (T3n).
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
81
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Figure 50:
CK# CK
tIS tIH tCK tCH tCL
Bank Write - With Auto Precharge
T0 T1 T2 T3 T4n T4 T4n T5 T5n T6 T7 T8
CKE
tIS tIH ACT tIS tIH Col n NOP5 WRITE2 NOP5 NOP5 NOP5 NOP5 NOP5
COMMAND4
NOP5
x4: A0-A9, A11 x8: A0-AA9 x16: A0-AA8 x8: A11 x16: A9, A11 A10
tIS
RA
RA 3 RA tIH Bank x tRCD tRAS tDQSS (NOM) tWR tRP tIS tIH
BA0, BA1
Bank x
DQS
tWPRES tWPRE
7
tDQSL
tDQSH tWPST
DQ1 DM
tDS
DI b
tDH
DON'T CARE
TRANSITIONING DATA
Notes: 1. DIn = data-out from column n; subsequent elements are provided in the programmed order. 2. BL = 4 in the case shown. 3. Enable auto precharge. 4. ACT = ACTIVE, RA = Row Address, BA = Bank Address. 5. NOP commands are shown for ease of illustration; other commands may be valid at these times. 6. See Figure 43, Initialize and Load Mode Registers, on page 75 for detailed DQ timing. 7. Although not requird by the Micron device, JEDEC specifies that DQS be a valid HIGH, LOW or some point on a valid transition on or before this clock edge (T3n).
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
82
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Timing Diagrams
Figure 51:
CK# CK
tIS tIH tCK tCH tCL
Write - DM Operation
T0 T1 T2 T3 T3n T4 T4n T5 T5n T6 T7 T8
CKE
tIS tIH ACT tIS tIH Col n NOP6 WRITE2 NOP6 NOP6 NOP6 NOP6 PRE
COMMAND5 x4: A0-AA9, A11 x8: A0-AA9 x16: A0-AA8 x8: A11 x16: A9, A11
NOP6
RA
RA tIS tIH
ALL BANKS
A10
RA tIS tIH
3
ONE BANK
BA0, BA1
Bank x tRCD tRAS
Bank x
Bank x4
tWR tRP
tDQSS (NOM)
DQS
tWPRES tWPRE
8
tDQSL
tDQSH tWPST
DQ1 DM
tDS
DI b
tDH
DON'T CARE
TRANSITIONING DATA
Notes: 1. 2. 3. 4. 5. 6.
DIn = data-in from column n; subsequent elements are provided in the programmed order. BL = 4 in the case shown. Disable auto precharge. "Don't Care" if A10 is HIGH at T8. PRE = PRECHARGE, ACT = ACTIVE, RA = Row Address, BA = Bank Address. NOP commands are shown for ease of illustration; other commands may be valid at these times. 7. See Figure 43, Initialize and Load Mode Registers, on page 75 for detailed DQ timing. 8. Although not requird by the Micron device, JEDEC specifies that DQS be a valid HIGH, LOW or some point on a valid transition on or before this clock edge (T3n).
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
83
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16 DDR SDRAM Package Dimensions
Package Dimensions
Figure 52: 66-Pin Plastic TSOP (400 mil)
22.22 0.08 0.71 0.65 TYP 0.32 .075 TYP 0.10 (2X) SEE DETAIL A
11.76 0.10 10.16 0.08
PIN #1 ID
+0.03 0.15 -0.02
GAGE PLANE
0.25
0.10 0.10 1.20 MAX
+0.10 -0.05 0.80 TYP 0.50 0.10 DETAIL A
Notes: 1. All dimensions are in millimeters. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.
(R)
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
PDF: 09005aef816fd013/Source: 09005aef816ce127 128MBDDRx4x8x16D_2.fm - Rev. C 4/05 EN
84
Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2004 Micron Technology, Inc. All rights reserved.

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